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Searched refs:REG_HDCP_BASE (Results 1 – 25 of 48) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdcp.h141 #define REG_HDCP_00_L (REG_HDCP_BASE + 0x00)
142 #define REG_HDCP_00_H (REG_HDCP_BASE + 0x01)
143 #define REG_HDCP_01_L (REG_HDCP_BASE + 0x02)
144 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x03)
145 #define REG_HDCP_02_L (REG_HDCP_BASE + 0x04)
146 #define REG_HDCP_02_H (REG_HDCP_BASE + 0x05)
147 #define REG_HDCP_03_L (REG_HDCP_BASE + 0x06)
148 #define REG_HDCP_03_H (REG_HDCP_BASE + 0x07)
149 #define REG_HDCP_09_L (REG_HDCP_BASE + 0x12)
150 #define REG_HDCP_09_H (REG_HDCP_BASE + 0x13)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdcp.h141 #define REG_HDCP_00_L (REG_HDCP_BASE + 0x00)
142 #define REG_HDCP_00_H (REG_HDCP_BASE + 0x01)
143 #define REG_HDCP_01_L (REG_HDCP_BASE + 0x02)
144 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x03)
145 #define REG_HDCP_02_L (REG_HDCP_BASE + 0x04)
146 #define REG_HDCP_02_H (REG_HDCP_BASE + 0x05)
147 #define REG_HDCP_03_L (REG_HDCP_BASE + 0x06)
148 #define REG_HDCP_03_H (REG_HDCP_BASE + 0x07)
149 #define REG_HDCP_09_L (REG_HDCP_BASE + 0x12)
150 #define REG_HDCP_09_H (REG_HDCP_BASE + 0x13)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdcp.h141 #define REG_HDCP_00_L (REG_HDCP_BASE + 0x00)
142 #define REG_HDCP_00_H (REG_HDCP_BASE + 0x01)
143 #define REG_HDCP_01_L (REG_HDCP_BASE + 0x02)
144 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x03)
145 #define REG_HDCP_02_L (REG_HDCP_BASE + 0x04)
146 #define REG_HDCP_02_H (REG_HDCP_BASE + 0x05)
147 #define REG_HDCP_03_L (REG_HDCP_BASE + 0x06)
148 #define REG_HDCP_03_H (REG_HDCP_BASE + 0x07)
149 #define REG_HDCP_09_L (REG_HDCP_BASE + 0x12)
150 #define REG_HDCP_09_H (REG_HDCP_BASE + 0x13)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdcp.h141 #define REG_HDCP_00_L (REG_HDCP_BASE + 0x00)
142 #define REG_HDCP_00_H (REG_HDCP_BASE + 0x01)
143 #define REG_HDCP_01_L (REG_HDCP_BASE + 0x02)
144 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x03)
145 #define REG_HDCP_02_L (REG_HDCP_BASE + 0x04)
146 #define REG_HDCP_02_H (REG_HDCP_BASE + 0x05)
147 #define REG_HDCP_03_L (REG_HDCP_BASE + 0x06)
148 #define REG_HDCP_03_H (REG_HDCP_BASE + 0x07)
149 #define REG_HDCP_09_L (REG_HDCP_BASE + 0x12)
150 #define REG_HDCP_09_H (REG_HDCP_BASE + 0x13)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdcp.h141 #define REG_HDCP_00_L (REG_HDCP_BASE + 0x00)
142 #define REG_HDCP_00_H (REG_HDCP_BASE + 0x01)
143 #define REG_HDCP_01_L (REG_HDCP_BASE + 0x02)
144 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x03)
145 #define REG_HDCP_02_L (REG_HDCP_BASE + 0x04)
146 #define REG_HDCP_02_H (REG_HDCP_BASE + 0x05)
147 #define REG_HDCP_03_L (REG_HDCP_BASE + 0x06)
148 #define REG_HDCP_03_H (REG_HDCP_BASE + 0x07)
149 #define REG_HDCP_09_L (REG_HDCP_BASE + 0x12)
150 #define REG_HDCP_09_H (REG_HDCP_BASE + 0x13)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdcp.h141 #define REG_HDCP_00_L (REG_HDCP_BASE + 0x00)
142 #define REG_HDCP_00_H (REG_HDCP_BASE + 0x01)
143 #define REG_HDCP_01_L (REG_HDCP_BASE + 0x02)
144 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x03)
145 #define REG_HDCP_02_L (REG_HDCP_BASE + 0x04)
146 #define REG_HDCP_02_H (REG_HDCP_BASE + 0x05)
147 #define REG_HDCP_03_L (REG_HDCP_BASE + 0x06)
148 #define REG_HDCP_03_H (REG_HDCP_BASE + 0x07)
149 #define REG_HDCP_09_L (REG_HDCP_BASE + 0x12)
150 #define REG_HDCP_09_H (REG_HDCP_BASE + 0x13)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdcp.h141 #define REG_HDCP_00_L (REG_HDCP_BASE + 0x00)
142 #define REG_HDCP_00_H (REG_HDCP_BASE + 0x01)
143 #define REG_HDCP_01_L (REG_HDCP_BASE + 0x02)
144 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x03)
145 #define REG_HDCP_02_L (REG_HDCP_BASE + 0x04)
146 #define REG_HDCP_02_H (REG_HDCP_BASE + 0x05)
147 #define REG_HDCP_03_L (REG_HDCP_BASE + 0x06)
148 #define REG_HDCP_03_H (REG_HDCP_BASE + 0x07)
149 #define REG_HDCP_09_L (REG_HDCP_BASE + 0x12)
150 #define REG_HDCP_09_H (REG_HDCP_BASE + 0x13)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdcp.h141 #define REG_HDCP_00_L (REG_HDCP_BASE + 0x00)
142 #define REG_HDCP_00_H (REG_HDCP_BASE + 0x01)
143 #define REG_HDCP_01_L (REG_HDCP_BASE + 0x02)
144 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x03)
145 #define REG_HDCP_02_L (REG_HDCP_BASE + 0x04)
146 #define REG_HDCP_02_H (REG_HDCP_BASE + 0x05)
147 #define REG_HDCP_03_L (REG_HDCP_BASE + 0x06)
148 #define REG_HDCP_03_H (REG_HDCP_BASE + 0x07)
149 #define REG_HDCP_09_L (REG_HDCP_BASE + 0x12)
150 #define REG_HDCP_09_H (REG_HDCP_BASE + 0x13)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdcp.h141 #define REG_HDCP_00_L (REG_HDCP_BASE + 0x00)
142 #define REG_HDCP_00_H (REG_HDCP_BASE + 0x01)
143 #define REG_HDCP_01_L (REG_HDCP_BASE + 0x02)
144 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x03)
145 #define REG_HDCP_02_L (REG_HDCP_BASE + 0x04)
146 #define REG_HDCP_02_H (REG_HDCP_BASE + 0x05)
147 #define REG_HDCP_03_L (REG_HDCP_BASE + 0x06)
148 #define REG_HDCP_03_H (REG_HDCP_BASE + 0x07)
149 #define REG_HDCP_09_L (REG_HDCP_BASE + 0x12)
150 #define REG_HDCP_09_H (REG_HDCP_BASE + 0x13)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdcp.h141 #define REG_HDCP_00_L (REG_HDCP_BASE + 0x00)
142 #define REG_HDCP_00_H (REG_HDCP_BASE + 0x01)
143 #define REG_HDCP_01_L (REG_HDCP_BASE + 0x02)
144 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x03)
145 #define REG_HDCP_02_L (REG_HDCP_BASE + 0x04)
146 #define REG_HDCP_02_H (REG_HDCP_BASE + 0x05)
147 #define REG_HDCP_03_L (REG_HDCP_BASE + 0x06)
148 #define REG_HDCP_03_H (REG_HDCP_BASE + 0x07)
149 #define REG_HDCP_09_L (REG_HDCP_BASE + 0x12)
150 #define REG_HDCP_09_H (REG_HDCP_BASE + 0x13)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdcp.h141 #define REG_HDCP_00_L (REG_HDCP_BASE + 0x00)
142 #define REG_HDCP_00_H (REG_HDCP_BASE + 0x01)
143 #define REG_HDCP_01_L (REG_HDCP_BASE + 0x02)
144 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x03)
145 #define REG_HDCP_02_L (REG_HDCP_BASE + 0x04)
146 #define REG_HDCP_02_H (REG_HDCP_BASE + 0x05)
147 #define REG_HDCP_03_L (REG_HDCP_BASE + 0x06)
148 #define REG_HDCP_03_H (REG_HDCP_BASE + 0x07)
149 #define REG_HDCP_09_L (REG_HDCP_BASE + 0x12)
150 #define REG_HDCP_09_H (REG_HDCP_BASE + 0x13)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdcp.h141 #define REG_HDCP_00_L (REG_HDCP_BASE + 0x00)
142 #define REG_HDCP_00_H (REG_HDCP_BASE + 0x01)
143 #define REG_HDCP_01_L (REG_HDCP_BASE + 0x02)
144 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x03)
145 #define REG_HDCP_02_L (REG_HDCP_BASE + 0x04)
146 #define REG_HDCP_02_H (REG_HDCP_BASE + 0x05)
147 #define REG_HDCP_03_L (REG_HDCP_BASE + 0x06)
148 #define REG_HDCP_03_H (REG_HDCP_BASE + 0x07)
149 #define REG_HDCP_09_L (REG_HDCP_BASE + 0x12)
150 #define REG_HDCP_09_H (REG_HDCP_BASE + 0x13)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdcp.h141 #define REG_HDCP_00_L (REG_HDCP_BASE + 0x00)
142 #define REG_HDCP_00_H (REG_HDCP_BASE + 0x01)
143 #define REG_HDCP_01_L (REG_HDCP_BASE + 0x02)
144 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x03)
145 #define REG_HDCP_02_L (REG_HDCP_BASE + 0x04)
146 #define REG_HDCP_02_H (REG_HDCP_BASE + 0x05)
147 #define REG_HDCP_03_L (REG_HDCP_BASE + 0x06)
148 #define REG_HDCP_03_H (REG_HDCP_BASE + 0x07)
149 #define REG_HDCP_09_L (REG_HDCP_BASE + 0x12)
150 #define REG_HDCP_09_H (REG_HDCP_BASE + 0x13)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdcp.h111 #define REG_HDCP_00_L (REG_HDCP_BASE + 0x00)
112 #define REG_HDCP_00_H (REG_HDCP_BASE + 0x01)
113 #define REG_HDCP_01_L (REG_HDCP_BASE + 0x02)
114 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x03)
115 #define REG_HDCP_02_L (REG_HDCP_BASE + 0x04)
116 #define REG_HDCP_02_H (REG_HDCP_BASE + 0x05)
117 #define REG_HDCP_03_L (REG_HDCP_BASE + 0x06)
118 #define REG_HDCP_03_H (REG_HDCP_BASE + 0x07)
119 #define REG_HDCP_09_L (REG_HDCP_BASE + 0x12)
120 #define REG_HDCP_09_H (REG_HDCP_BASE + 0x13)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdcp.h111 #define REG_HDCP_00_L (REG_HDCP_BASE + 0x00)
112 #define REG_HDCP_00_H (REG_HDCP_BASE + 0x01)
113 #define REG_HDCP_01_L (REG_HDCP_BASE + 0x02)
114 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x03)
115 #define REG_HDCP_02_L (REG_HDCP_BASE + 0x04)
116 #define REG_HDCP_02_H (REG_HDCP_BASE + 0x05)
117 #define REG_HDCP_03_L (REG_HDCP_BASE + 0x06)
118 #define REG_HDCP_03_H (REG_HDCP_BASE + 0x07)
119 #define REG_HDCP_09_L (REG_HDCP_BASE + 0x12)
120 #define REG_HDCP_09_H (REG_HDCP_BASE + 0x13)
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/cec/include/
H A Dcec_hwreg.h124 #define REG_HDCP_BASE 0x110AC0UL // HDCP started from 0xC0 macro
161 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x02)
162 #define REG_HDCP_15_L (REG_HDCP_BASE + 0x2A)
163 #define REG_HDCP_15_H (REG_HDCP_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/cec/include/
H A Dcec_hwreg.h124 #define REG_HDCP_BASE 0x110AC0UL // HDCP started from 0xC0 macro
161 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x02)
162 #define REG_HDCP_15_L (REG_HDCP_BASE + 0x2A)
163 #define REG_HDCP_15_H (REG_HDCP_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/cec/include/
H A Dcec_hwreg.h124 #define REG_HDCP_BASE 0x110AC0UL // HDCP started from 0xC0 macro
161 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x02)
162 #define REG_HDCP_15_L (REG_HDCP_BASE + 0x2A)
163 #define REG_HDCP_15_H (REG_HDCP_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/cec/include/
H A Dcec_hwreg.h124 #define REG_HDCP_BASE 0x110AC0 // HDCP started from 0xC0 macro
158 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x02)
159 #define REG_HDCP_15_L (REG_HDCP_BASE + 0x2A)
160 #define REG_HDCP_15_H (REG_HDCP_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/cec/include/
H A Dcec_hwreg.h124 #define REG_HDCP_BASE 0x110AC0UL // HDCP started from 0xC0 macro
161 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x02)
162 #define REG_HDCP_15_L (REG_HDCP_BASE + 0x2A)
163 #define REG_HDCP_15_H (REG_HDCP_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/cec/include/
H A Dcec_hwreg.h124 #define REG_HDCP_BASE 0x110AC0UL // HDCP started from 0xC0 macro
161 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x02)
162 #define REG_HDCP_15_L (REG_HDCP_BASE + 0x2A)
163 #define REG_HDCP_15_H (REG_HDCP_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/cec/include/
H A Dcec_hwreg.h124 #define REG_HDCP_BASE 0x110AC0UL // HDCP started from 0xC0 macro
161 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x02)
162 #define REG_HDCP_15_L (REG_HDCP_BASE + 0x2A)
163 #define REG_HDCP_15_H (REG_HDCP_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/cec/include/
H A Dcec_hwreg.h124 #define REG_HDCP_BASE 0x110AC0UL // HDCP started from 0xC0 macro
161 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x02)
162 #define REG_HDCP_15_L (REG_HDCP_BASE + 0x2A)
163 #define REG_HDCP_15_H (REG_HDCP_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/cec/include/
H A Dcec_hwreg.h124 #define REG_HDCP_BASE 0x110AC0UL // HDCP started from 0xC0 macro
161 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x02)
162 #define REG_HDCP_15_L (REG_HDCP_BASE + 0x2A)
163 #define REG_HDCP_15_H (REG_HDCP_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/cec/include/
H A Dcec_hwreg.h124 #define REG_HDCP_BASE 0x110AC0 // HDCP started from 0xC0 macro
158 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x02)
159 #define REG_HDCP_15_L (REG_HDCP_BASE + 0x2A)
160 #define REG_HDCP_15_H (REG_HDCP_BASE + 0x2B)

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