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Searched refs:REG_HDCP1_BASE (Results 1 – 25 of 46) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dhwreg_hdcp.h134 #define REG_HDCP1_1C_L (REG_HDCP1_BASE + 0x38)
135 #define REG_HDCP1_1C_H (REG_HDCP1_BASE + 0x39)
136 #define REG_HDCP1_15_L (REG_HDCP1_BASE + 0x2A)
137 #define REG_HDCP1_15_H (REG_HDCP1_BASE + 0x2B)
138 #define REG_HDCP1_1B_L (REG_HDCP1_BASE + 0x36)
139 #define REG_HDCP1_1B_H (REG_HDCP1_BASE + 0x37)
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dhwreg_hdcp.h134 #define REG_HDCP1_1C_L (REG_HDCP1_BASE + 0x38)
135 #define REG_HDCP1_1C_H (REG_HDCP1_BASE + 0x39)
136 #define REG_HDCP1_15_L (REG_HDCP1_BASE + 0x2A)
137 #define REG_HDCP1_15_H (REG_HDCP1_BASE + 0x2B)
138 #define REG_HDCP1_1B_L (REG_HDCP1_BASE + 0x36)
139 #define REG_HDCP1_1B_H (REG_HDCP1_BASE + 0x37)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/messi/cec/include/
H A Dcec_hwreg.h128 #define REG_HDCP1_BASE 0x1133C0UL // HDCP started from 0xC0 macro
164 #define REG_HDCP1_01_H (REG_HDCP1_BASE + 0x02)
165 #define REG_HDCP1_15_L (REG_HDCP1_BASE + 0x2A)
166 #define REG_HDCP1_15_H (REG_HDCP1_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maserati/cec/include/
H A Dcec_hwreg.h128 #define REG_HDCP1_BASE 0x1133C0UL // HDCP started from 0xC0 macro
164 #define REG_HDCP1_01_H (REG_HDCP1_BASE + 0x02)
165 #define REG_HDCP1_15_L (REG_HDCP1_BASE + 0x2A)
166 #define REG_HDCP1_15_H (REG_HDCP1_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/cec/include/
H A Dcec_hwreg.h128 #define REG_HDCP1_BASE 0x1133C0UL // HDCP started from 0xC0 macro
164 #define REG_HDCP1_01_H (REG_HDCP1_BASE + 0x02)
165 #define REG_HDCP1_15_L (REG_HDCP1_BASE + 0x2A)
166 #define REG_HDCP1_15_H (REG_HDCP1_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mustang/cec/include/
H A Dcec_hwreg.h128 #define REG_HDCP1_BASE 0x1133C0 // HDCP started from 0xC0 macro
161 #define REG_HDCP1_01_H (REG_HDCP1_BASE + 0x02)
162 #define REG_HDCP1_15_L (REG_HDCP1_BASE + 0x2A)
163 #define REG_HDCP1_15_H (REG_HDCP1_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/macan/cec/include/
H A Dcec_hwreg.h128 #define REG_HDCP1_BASE 0x1133C0UL // HDCP started from 0xC0 macro
164 #define REG_HDCP1_01_H (REG_HDCP1_BASE + 0x02)
165 #define REG_HDCP1_15_L (REG_HDCP1_BASE + 0x2A)
166 #define REG_HDCP1_15_H (REG_HDCP1_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/cec/include/
H A Dcec_hwreg.h128 #define REG_HDCP1_BASE 0x1133C0UL // HDCP started from 0xC0 macro
164 #define REG_HDCP1_01_H (REG_HDCP1_BASE + 0x02)
165 #define REG_HDCP1_15_L (REG_HDCP1_BASE + 0x2A)
166 #define REG_HDCP1_15_H (REG_HDCP1_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mooney/cec/include/
H A Dcec_hwreg.h128 #define REG_HDCP1_BASE 0x1133C0UL // HDCP started from 0xC0 macro
164 #define REG_HDCP1_01_H (REG_HDCP1_BASE + 0x02)
165 #define REG_HDCP1_15_L (REG_HDCP1_BASE + 0x2A)
166 #define REG_HDCP1_15_H (REG_HDCP1_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/manhattan/cec/include/
H A Dcec_hwreg.h128 #define REG_HDCP1_BASE 0x1133C0UL // HDCP started from 0xC0 macro
164 #define REG_HDCP1_01_H (REG_HDCP1_BASE + 0x02)
165 #define REG_HDCP1_15_L (REG_HDCP1_BASE + 0x2A)
166 #define REG_HDCP1_15_H (REG_HDCP1_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/cec/include/
H A Dcec_hwreg.h128 #define REG_HDCP1_BASE 0x1133C0UL // HDCP started from 0xC0 macro
164 #define REG_HDCP1_01_H (REG_HDCP1_BASE + 0x02)
165 #define REG_HDCP1_15_L (REG_HDCP1_BASE + 0x2A)
166 #define REG_HDCP1_15_H (REG_HDCP1_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maldives/cec/include/
H A Dcec_hwreg.h128 #define REG_HDCP1_BASE 0x1133C0 // HDCP started from 0xC0 macro
161 #define REG_HDCP1_01_H (REG_HDCP1_BASE + 0x02)
162 #define REG_HDCP1_15_L (REG_HDCP1_BASE + 0x2A)
163 #define REG_HDCP1_15_H (REG_HDCP1_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/cec/include/
H A Dcec_hwreg.h128 #define REG_HDCP1_BASE 0x1133C0UL // HDCP started from 0xC0 macro
164 #define REG_HDCP1_01_H (REG_HDCP1_BASE + 0x02)
165 #define REG_HDCP1_15_L (REG_HDCP1_BASE + 0x2A)
166 #define REG_HDCP1_15_H (REG_HDCP1_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/cec/include/
H A Dcec_hwreg.h128 #define REG_HDCP1_BASE 0x1133C0UL // HDCP started from 0xC0 macro
164 #define REG_HDCP1_01_H (REG_HDCP1_BASE + 0x02)
165 #define REG_HDCP1_15_L (REG_HDCP1_BASE + 0x2A)
166 #define REG_HDCP1_15_H (REG_HDCP1_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/mainz/cec/include/
H A Dcec_hwreg.h128 #define REG_HDCP1_BASE 0x1133C0UL // HDCP started from 0xC0 macro
164 #define REG_HDCP1_01_H (REG_HDCP1_BASE + 0x02)
165 #define REG_HDCP1_15_L (REG_HDCP1_BASE + 0x2A)
166 #define REG_HDCP1_15_H (REG_HDCP1_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7821/cec/include/
H A Dcec_hwreg.h128 #define REG_HDCP1_BASE 0x1133C0UL // HDCP started from 0xC0 macro
164 #define REG_HDCP1_01_H (REG_HDCP1_BASE + 0x02)
165 #define REG_HDCP1_15_L (REG_HDCP1_BASE + 0x2A)
166 #define REG_HDCP1_15_H (REG_HDCP1_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/cec/include/
H A Dcec_hwreg.h128 #define REG_HDCP1_BASE 0x1133C0UL // HDCP started from 0xC0 macro
164 #define REG_HDCP1_01_H (REG_HDCP1_BASE + 0x02)
165 #define REG_HDCP1_15_L (REG_HDCP1_BASE + 0x2A)
166 #define REG_HDCP1_15_H (REG_HDCP1_BASE + 0x2B)
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdcp.h164 #define REG_HDCP1_1C_L (REG_HDCP1_BASE + 0x38)
165 #define REG_HDCP1_1C_H (REG_HDCP1_BASE + 0x39)
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdcp.h164 #define REG_HDCP1_1C_L (REG_HDCP1_BASE + 0x38)
165 #define REG_HDCP1_1C_H (REG_HDCP1_BASE + 0x39)
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdcp.h164 #define REG_HDCP1_1C_L (REG_HDCP1_BASE + 0x38)
165 #define REG_HDCP1_1C_H (REG_HDCP1_BASE + 0x39)
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdcp.h164 #define REG_HDCP1_1C_L (REG_HDCP1_BASE + 0x38)
165 #define REG_HDCP1_1C_H (REG_HDCP1_BASE + 0x39)
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdcp.h164 #define REG_HDCP1_1C_L (REG_HDCP1_BASE + 0x38)
165 #define REG_HDCP1_1C_H (REG_HDCP1_BASE + 0x39)
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdcp.h164 #define REG_HDCP1_1C_L (REG_HDCP1_BASE + 0x38)
165 #define REG_HDCP1_1C_H (REG_HDCP1_BASE + 0x39)
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdcp.h164 #define REG_HDCP1_1C_L (REG_HDCP1_BASE + 0x38)
165 #define REG_HDCP1_1C_H (REG_HDCP1_BASE + 0x39)
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdcp.h164 #define REG_HDCP1_1C_L (REG_HDCP1_BASE + 0x38)
165 #define REG_HDCP1_1C_H (REG_HDCP1_BASE + 0x39)

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