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Searched refs:REG_FRC_BK3F_11_L (Results 1 – 11 of 11) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_frc.c655 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(2)); // miu_sel from register in MHal_FRC_IPM_SetBaseAddr()
663 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(3)); // miu_sel from register in MHal_FRC_IPM_SetBaseAddr()
671 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(0)); // miu_sel from register in MHal_FRC_IPM_SetBaseAddr()
679 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(1)); // miu_sel from register in MHal_FRC_IPM_SetBaseAddr()
714 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(2)); // miu_sel from register in MHal_FRC_IPM_R_SetBaseAddr()
722 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(3)); // miu_sel from register in MHal_FRC_IPM_R_SetBaseAddr()
730 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(0)); // miu_sel from register in MHal_FRC_IPM_R_SetBaseAddr()
738 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(1)); // miu_sel from register in MHal_FRC_IPM_R_SetBaseAddr()
771 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, (BIT(4)|BIT(6)|BIT(8))); // miu_sel from register in MHal_FRC_OPM_SetBaseAddr()
781 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, (BIT(5)|BIT(7)|BIT(9))); // miu_sel from register in MHal_FRC_OPM_SetBaseAddr()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_frc.c836 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(2)); // miu_sel from register in MHal_FRC_IPM_SetBaseAddr()
851 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(3)); // miu_sel from register in MHal_FRC_IPM_SetBaseAddr()
859 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(0)); // miu_sel from register in MHal_FRC_IPM_SetBaseAddr()
874 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(1)); // miu_sel from register in MHal_FRC_IPM_SetBaseAddr()
912 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(2)); // miu_sel from register in MHal_FRC_IPM_R_SetBaseAddr()
920 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(3)); // miu_sel from register in MHal_FRC_IPM_R_SetBaseAddr()
935 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(0)); // miu_sel from register in MHal_FRC_IPM_R_SetBaseAddr()
943 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(1)); // miu_sel from register in MHal_FRC_IPM_R_SetBaseAddr()
983 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, (BIT(4)|BIT(6)|BIT(8))); // miu_sel from register in MHal_FRC_OPM_SetBaseAddr()
993 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, (BIT(5)|BIT(7)|BIT(9))); // miu_sel from register in MHal_FRC_OPM_SetBaseAddr()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_frc.c819 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(2)); // miu_sel from register in MHal_FRC_IPM_SetBaseAddr()
834 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(3)); // miu_sel from register in MHal_FRC_IPM_SetBaseAddr()
842 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(0)); // miu_sel from register in MHal_FRC_IPM_SetBaseAddr()
857 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(1)); // miu_sel from register in MHal_FRC_IPM_SetBaseAddr()
895 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(2)); // miu_sel from register in MHal_FRC_IPM_R_SetBaseAddr()
903 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(3)); // miu_sel from register in MHal_FRC_IPM_R_SetBaseAddr()
918 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(0)); // miu_sel from register in MHal_FRC_IPM_R_SetBaseAddr()
926 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(1)); // miu_sel from register in MHal_FRC_IPM_R_SetBaseAddr()
966 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, (BIT(4)|BIT(6)|BIT(8))); // miu_sel from register in MHal_FRC_OPM_SetBaseAddr()
976 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, (BIT(5)|BIT(7)|BIT(9))); // miu_sel from register in MHal_FRC_OPM_SetBaseAddr()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_frc.c809 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(2)); // miu_sel from register in MHal_FRC_IPM_SetBaseAddr()
849 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(3)); // miu_sel from register in MHal_FRC_IPM_SetBaseAddr()
857 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(0)); // miu_sel from register in MHal_FRC_IPM_SetBaseAddr()
897 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(1)); // miu_sel from register in MHal_FRC_IPM_SetBaseAddr()
947 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(2)); // miu_sel from register in MHal_FRC_IPM_R_SetBaseAddr()
955 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(3)); // miu_sel from register in MHal_FRC_IPM_R_SetBaseAddr()
995 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(0)); // miu_sel from register in MHal_FRC_IPM_R_SetBaseAddr()
1003 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(1)); // miu_sel from register in MHal_FRC_IPM_R_SetBaseAddr()
1080 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, (BIT(4)|BIT(6)|BIT(8))); // miu_sel from register in MHal_FRC_OPM_SetBaseAddr()
1115 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, (BIT(5)|BIT(7)|BIT(9))); // miu_sel from register in MHal_FRC_OPM_SetBaseAddr()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_frc.c809 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(2)); // miu_sel from register in MHal_FRC_IPM_SetBaseAddr()
849 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(3)); // miu_sel from register in MHal_FRC_IPM_SetBaseAddr()
857 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(0)); // miu_sel from register in MHal_FRC_IPM_SetBaseAddr()
897 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(1)); // miu_sel from register in MHal_FRC_IPM_SetBaseAddr()
947 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(2)); // miu_sel from register in MHal_FRC_IPM_R_SetBaseAddr()
955 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(3)); // miu_sel from register in MHal_FRC_IPM_R_SetBaseAddr()
995 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(0)); // miu_sel from register in MHal_FRC_IPM_R_SetBaseAddr()
1003 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, BIT(1)); // miu_sel from register in MHal_FRC_IPM_R_SetBaseAddr()
1080 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, (BIT(4)|BIT(6)|BIT(8))); // miu_sel from register in MHal_FRC_OPM_SetBaseAddr()
1115 W2BYTEMSK(REG_FRC_BK3F_11_L, 0x00, (BIT(5)|BIT(7)|BIT(9))); // miu_sel from register in MHal_FRC_OPM_SetBaseAddr()
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_frc_map.h1961 #define REG_FRC_BK3F_11_L FRC_PK_L_(0x3F, 0x11) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_frc_map.h1961 #define REG_FRC_BK3F_11_L FRC_PK_L_(0x3F, 0x11) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_frc_map.h1961 #define REG_FRC_BK3F_11_L FRC_PK_L_(0x3F, 0x11) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_frc_map.h1961 #define REG_FRC_BK3F_11_L FRC_PK_L_(0x3F, 0x11) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_frc_map.h1961 #define REG_FRC_BK3F_11_L FRC_PK_L_(0x3F, 0x11) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_frc_map.h1961 #define REG_FRC_BK3F_11_L FRC_PK_L_(0x3F, 0x11) macro