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Searched refs:REG_FRC_BK226_61 (Results 1 – 25 of 50) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A DMaserati_2D_4K2K.c340 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x72, 0xff); // reg_MFC_enable in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
761 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_2D_4K2K_2D_FHD_YUV()
1182 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x72, 0xff); // reg_MFC_enable in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1603 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_2D_4K2K_2D_4K2K_YUV()
2024 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x72, 0xff); // reg_MFC_enable in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2445 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_2D_4K2K_2D_2205_YUV()
H A DMaserati_2D_FHD.c340 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x72, 0xff); // reg_MFC_enable in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
761 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_480.c340 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x72, 0xff); // reg_MFC_enable in MFC_3D_2D_480_2D_480_RGB_BYPASS()
790 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c340 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x72, 0xff); // reg_MFC_enable in MFC_3D_2D_576_2D_576_RGB_BYPASS()
790 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_2D_576_2D_576_YUV()
H A DMaserati_2D_720.c340 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x72, 0xff); // reg_MFC_enable in MFC_3D_2D_720_2D_720_RGB_BYPASS()
790 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_2D_720_2D_720_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A DMaserati_2D_4K2K.c340 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x72, 0xff); // reg_MFC_enable in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
761 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_2D_4K2K_2D_FHD_YUV()
1182 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x72, 0xff); // reg_MFC_enable in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1603 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_2D_4K2K_2D_4K2K_YUV()
2024 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x72, 0xff); // reg_MFC_enable in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2445 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_2D_4K2K_2D_2205_YUV()
H A DMaserati_2D_FHD.c340 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x72, 0xff); // reg_MFC_enable in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
761 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_720.c340 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x72, 0xff); // reg_MFC_enable in MFC_3D_2D_720_2D_720_RGB_BYPASS()
790 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_2D_720_2D_720_YUV()
H A DMaserati_2D_480.c340 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x72, 0xff); // reg_MFC_enable in MFC_3D_2D_480_2D_480_RGB_BYPASS()
790 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c340 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x72, 0xff); // reg_MFC_enable in MFC_3D_2D_576_2D_576_RGB_BYPASS()
790 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_2D_576_2D_576_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A DMaxim_2D_4K2K.c283 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x72, 0xff); // reg_MFC_enable in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
627 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_2D_4K2K_2D_FHD_YUV()
971 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x72, 0xff); // reg_MFC_enable in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1315 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A DMaxim_2D_FHD.c283 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x72, 0xff); // reg_MFC_enable in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
627 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaxim_ACT_4K0_5K.c283 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaxim_FRC_ACT_4K0_5K_LLRR_240.c283 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_LLRR_240.c283 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaxim_ACT_4K1K.c283 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaxim_FRC_ACT_4K2K_120.c283 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_60.c283 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_120.c283 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A DMaxim_2D_4K2K.c283 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x72, 0xff); // reg_MFC_enable in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
627 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_2D_4K2K_2D_FHD_YUV()
971 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x72, 0xff); // reg_MFC_enable in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1315 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A DMaxim_2D_FHD.c283 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x72, 0xff); // reg_MFC_enable in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
627 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaxim_FRC_ACT_4K0_5K_LLRR_240.c283 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_120.c283 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_LLRR_240.c283 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_120.c283 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()

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