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Searched refs:REG_FRC_BK13D_31 (Results 1 – 25 of 54) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A DMaserati_2D_4K2K.c180 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
601 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_YUV()
1022 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1443 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1864 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2285 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_2205_YUV()
H A DMaserati_2D_FHD.c180 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
601 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_480.c180 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_480_2D_480_RGB_BYPASS()
630 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c180 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_576_2D_576_RGB_BYPASS()
630 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_576_2D_576_YUV()
H A DMaserati_2D_720.c180 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_720_2D_720_RGB_BYPASS()
630 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_720_2D_720_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A DMaserati_2D_4K2K.c180 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
601 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_YUV()
1022 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1443 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1864 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2285 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_2205_YUV()
H A DMaserati_2D_FHD.c180 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
601 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_720.c180 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_720_2D_720_RGB_BYPASS()
630 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_720_2D_720_YUV()
H A DMaserati_2D_480.c180 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_480_2D_480_RGB_BYPASS()
630 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c180 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_576_2D_576_RGB_BYPASS()
630 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_576_2D_576_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A DMaxim_2D_4K2K.c123 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
467 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_YUV()
811 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1155 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A DMaxim_2D_FHD.c123 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
467 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaxim_ACT_4K0_5K.c123 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaxim_FRC_ACT_4K0_5K_LLRR_240.c123 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x02, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_LLRR_240.c123 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaxim_ACT_4K1K.c123 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaxim_FRC_ACT_4K2K_120.c123 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A DMaxim_2D_4K2K.c123 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
467 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_YUV()
811 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1155 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A DMaxim_2D_FHD.c123 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
467 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaxim_FRC_ACT_4K0_5K_LLRR_240.c123 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x02, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_120.c123 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_LLRR_240.c123 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_120.c123 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x04, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A DManhattan_2D_4K2K.c191 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
659 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_YUV()
1127 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1595 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A DManhattan_2D_4K2K.c191 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
659 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_FHD_YUV()
1127 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1595 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2 in MFC_3D_2D_4K2K_2D_4K2K_YUV()

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