REG_FRC_BK13A_CD (reference) in projects: utopia

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Searched refs:REG_FRC_BK13A_CD (Results 1 – 25 of 54) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A D	Maserati_2D_4K2K.c	184 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 205 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 605 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 626 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 1026 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1047 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1447 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1468 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1868 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() 1889 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() [all …]
H A D	Maserati_2D_FHD.c	`184 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 205 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 605 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_YUV() 626 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maserati_2D_480.c	`184 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_480_2D_480_RGB_BYPASS() 205 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_480_2D_480_RGB_BYPASS() 634 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_480_2D_480_YUV() 655 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_480_2D_480_YUV()`
H A D	Maserati_2D_576.c	`184 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_576_2D_576_RGB_BYPASS() 205 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_576_2D_576_RGB_BYPASS() 634 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_576_2D_576_YUV() 655 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_576_2D_576_YUV()`
H A D	Maserati_2D_720.c	`184 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_720_2D_720_RGB_BYPASS() 205 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_720_2D_720_RGB_BYPASS() 634 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_720_2D_720_YUV() 655 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_720_2D_720_YUV()`
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A D	Maserati_2D_4K2K.c	184 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 205 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 605 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 626 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 1026 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1047 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1447 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1468 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1868 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() 1889 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() [all …]
H A D	Maserati_2D_FHD.c	`184 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 205 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 605 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_YUV() 626 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maserati_2D_720.c	`184 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_720_2D_720_RGB_BYPASS() 205 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_720_2D_720_RGB_BYPASS() 634 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_720_2D_720_YUV() 655 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_720_2D_720_YUV()`
H A D	Maserati_2D_480.c	`184 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_480_2D_480_RGB_BYPASS() 205 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_480_2D_480_RGB_BYPASS() 634 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_480_2D_480_YUV() 655 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_480_2D_480_YUV()`
H A D	Maserati_2D_576.c	`184 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_576_2D_576_RGB_BYPASS() 205 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_576_2D_576_RGB_BYPASS() 634 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_576_2D_576_YUV() 655 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_576_2D_576_YUV()`
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A D	Maxim_2D_4K2K.c	127 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 148 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 471 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 492 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 815 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 836 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1159 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1180 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A D	Maxim_2D_FHD.c	`127 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 148 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 471 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_YUV() 492 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maxim_ACT_4K0_5K.c	`127 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC() 148 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()`
H A D	Maxim_FRC_ACT_4K0_5K_LLRR_240.c	`127 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB() 148 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x02, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_LLRR_240.c	`127 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB() 148 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_ACT_4K1K.c	`127 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC() 148 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()`
H A D	Maxim_FRC_ACT_4K2K_120.c	`127 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB() 148 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()`
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A D	Maxim_2D_4K2K.c	127 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 148 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 471 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 492 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 815 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 836 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1159 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1180 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A D	Maxim_2D_FHD.c	`127 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 148 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 471 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_FHD_2D_FHD_YUV() 492 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x04, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maxim_FRC_ACT_4K0_5K_LLRR_240.c	`127 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB() 148 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x02, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_PAS_4K2K_120.c	`127 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB() 148 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_LLRR_240.c	`127 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB() 148 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_120.c	`127 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB() 148 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()`
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A D	Manhattan_2D_4K2K.c	195 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 216 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 663 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 684 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 1131 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1152 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1599 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1620 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A D	Manhattan_2D_4K2K.c	195 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 216 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 663 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_FHD_YUV() 684 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_FHD_YUV() 1131 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1152 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1599 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1620 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new in MFC_3D_2D_4K2K_2D_4K2K_YUV()

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