REG_FRC_BK134_27 (reference) in projects: utopia

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Searched refs:REG_FRC_BK134_27 (Results 1 – 25 of 56) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A D	Maserati_2D_4K2K.c	253 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 256 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 674 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 677 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_FHD_YUV() 1095 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1098 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1516 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1519 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1937 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() 1940 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() [all …]
H A D	Maserati_2D_FHD.c	`253 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 256 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 674 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_FHD_2D_FHD_YUV() 677 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maserati_2D_480.c	`253 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_480_2D_480_RGB_BYPASS() 256 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_480_2D_480_RGB_BYPASS() 703 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_480_2D_480_YUV() 706 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_480_2D_480_YUV()`
H A D	Maserati_2D_576.c	`253 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_576_2D_576_RGB_BYPASS() 256 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_576_2D_576_RGB_BYPASS() 703 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_576_2D_576_YUV() 706 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_576_2D_576_YUV()`
H A D	Maserati_2D_720.c	`253 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_720_2D_720_RGB_BYPASS() 256 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_720_2D_720_RGB_BYPASS() 703 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_720_2D_720_YUV() 706 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_720_2D_720_YUV()`
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A D	Maserati_2D_4K2K.c	253 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 256 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 674 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 677 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_FHD_YUV() 1095 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1098 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1516 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1519 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1937 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() 1940 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS() [all …]
H A D	Maserati_2D_FHD.c	`253 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 256 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 674 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_FHD_2D_FHD_YUV() 677 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maserati_2D_720.c	`253 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_720_2D_720_RGB_BYPASS() 256 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_720_2D_720_RGB_BYPASS() 703 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_720_2D_720_YUV() 706 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_720_2D_720_YUV()`
H A D	Maserati_2D_480.c	`253 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_480_2D_480_RGB_BYPASS() 256 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_480_2D_480_RGB_BYPASS() 703 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_480_2D_480_YUV() 706 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_480_2D_480_YUV()`
H A D	Maserati_2D_576.c	`253 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_576_2D_576_RGB_BYPASS() 256 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_576_2D_576_RGB_BYPASS() 703 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_576_2D_576_YUV() 706 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_576_2D_576_YUV()`
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A D	Maxim_2D_4K2K.c	196 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 199 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 540 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 543 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_FHD_YUV() 884 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 887 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1228 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1231 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A D	Maxim_2D_FHD.c	`196 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 199 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 540 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_FHD_2D_FHD_YUV() 543 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maxim_ACT_4K0_5K.c	`196 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC() 199 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()`
H A D	Maxim_FRC_ACT_4K0_5K_LLRR_240.c	`196 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB() 199 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x01, 0x1f); // reg_ipm_turn_back_line in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_LLRR_240.c	`196 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB() 199 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_ACT_4K1K.c	`196 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC() 199 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()`
H A D	Maxim_FRC_ACT_4K2K_120.c	`196 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB() 199 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()`
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A D	Maxim_2D_4K2K.c	196 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 199 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 540 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 543 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_FHD_YUV() 884 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 887 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1228 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1231 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A D	Maxim_2D_FHD.c	`196 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 199 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS() 540 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_FHD_2D_FHD_YUV() 543 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_FHD_2D_FHD_YUV()`
H A D	Maxim_FRC_ACT_4K0_5K_LLRR_240.c	`196 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB() 199 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x01, 0x1f); // reg_ipm_turn_back_line in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_PAS_4K2K_120.c	`196 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB() 199 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_LLRR_240.c	`196 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB() 199 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()`
H A D	Maxim_FRC_ACT_4K1K_120.c	`196 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB() 199 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x02, 0x1f); // reg_ipm_turn_back_line in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()`
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A D	Manhattan_2D_4K2K.c	264 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 267 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 732 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 735 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_FHD_YUV() 1200 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1203 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1668 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1671 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_4K2K_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A D	Manhattan_2D_4K2K.c	264 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 267 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS() 732 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_FHD_YUV() 735 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_FHD_YUV() 1200 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1203 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS() 1668 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en in MFC_3D_2D_4K2K_2D_4K2K_YUV() 1671 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line in MFC_3D_2D_4K2K_2D_4K2K_YUV()

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