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Searched refs:REG_FRC_BK134_1C (Results 1 – 25 of 54) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A DMaserati_2D_4K2K.c129 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
550 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_FHD_YUV()
971 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1392 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1813 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2234 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_2205_YUV()
H A DMaserati_2D_FHD.c129 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0xc0, 0xff); // ipm_offset_f2 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
550 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0xc0, 0xff); // ipm_offset_f2 in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_480.c129 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0xc0, 0xff); // ipm_offset_f2 in MFC_3D_2D_480_2D_480_RGB_BYPASS()
579 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0xc0, 0xff); // ipm_offset_f2 in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c129 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0xc0, 0xff); // ipm_offset_f2 in MFC_3D_2D_576_2D_576_RGB_BYPASS()
579 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0xc0, 0xff); // ipm_offset_f2 in MFC_3D_2D_576_2D_576_YUV()
H A DMaserati_2D_720.c129 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0xc0, 0xff); // ipm_offset_f2 in MFC_3D_2D_720_2D_720_RGB_BYPASS()
579 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0xc0, 0xff); // ipm_offset_f2 in MFC_3D_2D_720_2D_720_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A DMaserati_2D_4K2K.c129 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
550 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_FHD_YUV()
971 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1392 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
1813 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_2205_RGB_BYPASS()
2234 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_2205_YUV()
H A DMaserati_2D_FHD.c129 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0xc0, 0xff); // ipm_offset_f2 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
550 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0xc0, 0xff); // ipm_offset_f2 in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_2D_720.c129 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0xc0, 0xff); // ipm_offset_f2 in MFC_3D_2D_720_2D_720_RGB_BYPASS()
579 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0xc0, 0xff); // ipm_offset_f2 in MFC_3D_2D_720_2D_720_YUV()
H A DMaserati_2D_480.c129 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0xc0, 0xff); // ipm_offset_f2 in MFC_3D_2D_480_2D_480_RGB_BYPASS()
579 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0xc0, 0xff); // ipm_offset_f2 in MFC_3D_2D_480_2D_480_YUV()
H A DMaserati_2D_576.c129 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0xc0, 0xff); // ipm_offset_f2 in MFC_3D_2D_576_2D_576_RGB_BYPASS()
579 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0xc0, 0xff); // ipm_offset_f2 in MFC_3D_2D_576_2D_576_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A DMaxim_2D_4K2K.c72 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
416 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_FHD_YUV()
760 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1104 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A DMaxim_2D_FHD.c72 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0xc0, 0xff); // ipm_offset_f2 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
416 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0xc0, 0xff); // ipm_offset_f2 in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaxim_ACT_4K0_5K.c72 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaxim_FRC_ACT_4K0_5K_LLRR_240.c72 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_LLRR_240.c72 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaxim_ACT_4K1K.c72 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaxim_FRC_ACT_4K2K_120.c72 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A DMaxim_2D_4K2K.c72 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
416 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_FHD_YUV()
760 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1104 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
H A DMaxim_2D_FHD.c72 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0xc0, 0xff); // ipm_offset_f2 in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
416 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0xc0, 0xff); // ipm_offset_f2 in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaxim_FRC_ACT_4K0_5K_LLRR_240.c72 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_PAS_4K2K_120.c72 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_LLRR_240.c72 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaxim_FRC_ACT_4K1K_120.c72 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A DManhattan_2D_4K2K.c140 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
608 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_FHD_YUV()
1076 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1544 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_4K2K_YUV()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A DManhattan_2D_4K2K.c140 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
608 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_FHD_YUV()
1076 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1544 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2 in MFC_3D_2D_4K2K_2D_4K2K_YUV()

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