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Searched refs:REG_FRC_BK119_10_L (Results 1 – 8 of 8) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_frc.c1109 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(3),BIT(3)); //ME1_X1 memory address limit enable in MHal_FRC_ME1_SetBaseAddr()
1121 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(4),BIT(4)); //ME1_S1 memory address limit enable in MHal_FRC_ME1_SetBaseAddr()
1158 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(5),BIT(5)); //ME2_X2 memory address limit enable in MHal_FRC_ME2_SetBaseAddr()
1170 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(6),BIT(6)); //ME2_Y2 memory address limit enable in MHal_FRC_ME2_SetBaseAddr()
1182 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(7),BIT(7)); //ME2_F2 memory address limit enable in MHal_FRC_ME2_SetBaseAddr()
1195 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(8),BIT(8)); //ME2_LOGO memory address limit enable in MHal_FRC_ME2_SetBaseAddr()
1243 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(2),BIT(2)); //HR memory address limit enable in MHal_FRC_Halo_SetBaseAddr()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_frc.c1092 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(3),BIT(3)); //ME1_X1 memory address limit enable in MHal_FRC_ME1_SetBaseAddr()
1104 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(4),BIT(4)); //ME1_S1 memory address limit enable in MHal_FRC_ME1_SetBaseAddr()
1141 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(5),BIT(5)); //ME2_X2 memory address limit enable in MHal_FRC_ME2_SetBaseAddr()
1153 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(6),BIT(6)); //ME2_Y2 memory address limit enable in MHal_FRC_ME2_SetBaseAddr()
1165 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(7),BIT(7)); //ME2_F2 memory address limit enable in MHal_FRC_ME2_SetBaseAddr()
1178 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(8),BIT(8)); //ME2_LOGO memory address limit enable in MHal_FRC_ME2_SetBaseAddr()
1226 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(2),BIT(2)); //HR memory address limit enable in MHal_FRC_Halo_SetBaseAddr()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_frc.c1294 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(3),BIT(3)); //ME1_X1 memory address limit enable in MHal_FRC_ME1_SetBaseAddr()
1306 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(4),BIT(4)); //ME1_S1 memory address limit enable in MHal_FRC_ME1_SetBaseAddr()
1371 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(5),BIT(5)); //ME2_X2 memory address limit enable in MHal_FRC_ME2_SetBaseAddr()
1383 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(6),BIT(6)); //ME2_Y2 memory address limit enable in MHal_FRC_ME2_SetBaseAddr()
1395 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(7),BIT(7)); //ME2_F2 memory address limit enable in MHal_FRC_ME2_SetBaseAddr()
1408 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(8),BIT(8)); //ME2_LOGO memory address limit enable in MHal_FRC_ME2_SetBaseAddr()
1484 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(2),BIT(2)); //HR memory address limit enable in MHal_FRC_Halo_SetBaseAddr()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_frc.c1294 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(3),BIT(3)); //ME1_X1 memory address limit enable in MHal_FRC_ME1_SetBaseAddr()
1306 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(4),BIT(4)); //ME1_S1 memory address limit enable in MHal_FRC_ME1_SetBaseAddr()
1371 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(5),BIT(5)); //ME2_X2 memory address limit enable in MHal_FRC_ME2_SetBaseAddr()
1383 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(6),BIT(6)); //ME2_Y2 memory address limit enable in MHal_FRC_ME2_SetBaseAddr()
1395 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(7),BIT(7)); //ME2_F2 memory address limit enable in MHal_FRC_ME2_SetBaseAddr()
1408 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(8),BIT(8)); //ME2_LOGO memory address limit enable in MHal_FRC_ME2_SetBaseAddr()
1484 W2BYTEMSK(REG_FRC_BK119_10_L, BIT(2),BIT(2)); //HR memory address limit enable in MHal_FRC_Halo_SetBaseAddr()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_frc_map.h5045 #define REG_FRC_BK119_10_L FRC_PK_L_(0x119, 0x10) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_frc_map.h5045 #define REG_FRC_BK119_10_L FRC_PK_L_(0x119, 0x10) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_frc_map.h5045 #define REG_FRC_BK119_10_L FRC_PK_L_(0x119, 0x10) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_frc_map.h5045 #define REG_FRC_BK119_10_L FRC_PK_L_(0x119, 0x10) macro