Searched refs:REG_CLKGEN2_DC0_SYNTH (Results 1 – 4 of 4) sorted by relevance
308 #define REG_CLKGEN2_DC0_SYNTH 0x30UL macro3670 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC2_CW_SEL; in HAL_TSP_SetSTCSynth()3673 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC2_CW_EN; in HAL_TSP_SetSTCSynth()3674 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC2_CW_EN; in HAL_TSP_SetSTCSynth()3675 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC2_CW_EN; in HAL_TSP_SetSTCSynth()3676 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC2_CW_SEL; in HAL_TSP_SetSTCSynth()3679 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_SEL; in HAL_TSP_SetSTCSynth()3682 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()3683 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()3684 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()[all …]
308 #define REG_CLKGEN2_DC0_SYNTH 0x30UL macro3653 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC2_CW_SEL; in HAL_TSP_SetSTCSynth()3656 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC2_CW_EN; in HAL_TSP_SetSTCSynth()3657 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC2_CW_EN; in HAL_TSP_SetSTCSynth()3658 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC2_CW_EN; in HAL_TSP_SetSTCSynth()3659 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC2_CW_SEL; in HAL_TSP_SetSTCSynth()3662 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_SEL; in HAL_TSP_SetSTCSynth()3665 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()3666 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()3667 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()[all …]
316 #define REG_CLKGEN2_DC0_SYNTH 0x30UL macro3749 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC2_CW_SEL; in HAL_TSP_SetSTCSynth()3752 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC2_CW_EN; in HAL_TSP_SetSTCSynth()3753 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC2_CW_EN; in HAL_TSP_SetSTCSynth()3754 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC2_CW_EN; in HAL_TSP_SetSTCSynth()3755 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC2_CW_SEL; in HAL_TSP_SetSTCSynth()3758 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_SEL; in HAL_TSP_SetSTCSynth()3761 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()3762 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()3763 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()[all …]
316 #define REG_CLKGEN2_DC0_SYNTH 0x30UL macro3710 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC2_CW_SEL; in HAL_TSP_SetSTCSynth()3713 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC2_CW_EN; in HAL_TSP_SetSTCSynth()3714 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC2_CW_EN; in HAL_TSP_SetSTCSynth()3715 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC2_CW_EN; in HAL_TSP_SetSTCSynth()3716 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC2_CW_SEL; in HAL_TSP_SetSTCSynth()3719 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_SEL; in HAL_TSP_SetSTCSynth()3722 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()3723 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) |= REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()3724 TSP_CLKGEN2_REG(REG_CLKGEN2_DC0_SYNTH) &= ~REG_CLKGEN2_STC3_CW_EN; in HAL_TSP_SetSTCSynth()[all …]