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Searched refs:REG_CKG_IDCLK3 (Results 1 – 25 of 38) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_mux.c463 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux << 2, CKG_IDCLK3_MASK); in Hal_SC_mux_set_dipwin_ip_mux()
727 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in Hal_SC_EnableCLK_for_DIP()
728 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
733 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_INVERT); // Not Invert in Hal_SC_EnableCLK_for_DIP()
734 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
H A Dmhal_dip.c734 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in HAL_XC_DIP_Init()
735 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_Init()
1399 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux, CKG_IDCLK3_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_mux.c463 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux << 2, CKG_IDCLK3_MASK); in Hal_SC_mux_set_dipwin_ip_mux()
722 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in Hal_SC_EnableCLK_for_DIP()
723 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
728 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_INVERT); // Not Invert in Hal_SC_EnableCLK_for_DIP()
729 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
H A Dmhal_dip.c732 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in HAL_XC_DIP_Init()
733 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_Init()
1397 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux, CKG_IDCLK3_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_mux.c463 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux << 2, CKG_IDCLK3_MASK); in Hal_SC_mux_set_dipwin_ip_mux()
713 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in Hal_SC_EnableCLK_for_DIP()
714 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
719 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_INVERT); // Not Invert in Hal_SC_EnableCLK_for_DIP()
720 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
H A Dmhal_dip.c1411 … MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in HAL_XC_DIP_Init()
1412 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Dis… in HAL_XC_DIP_Init()
1550 MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); in HAL_XC_DIP_EnableCaptureStream()
1739 …MDrv_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Disabl… in HAL_XC_DIP_ClearIntr()
1837 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_CpatureOneFrame2()
2162 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux, CKG_IDCLK3_MASK); in HAL_XC_DIP_SetMux()
4248 …MDrv_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Disabl… in HAL_XC_DIP_InterruptDetach()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_mux.c463 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux << 2, CKG_IDCLK3_MASK); in Hal_SC_mux_set_dipwin_ip_mux()
713 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in Hal_SC_EnableCLK_for_DIP()
714 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
719 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_INVERT); // Not Invert in Hal_SC_EnableCLK_for_DIP()
720 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_mux.c540 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux << 2, CKG_IDCLK3_MASK); in Hal_SC_mux_set_dipwin_ip_mux()
851 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in Hal_SC_EnableCLK_for_DIP()
852 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
857 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_INVERT); // Not Invert in Hal_SC_EnableCLK_for_DIP()
858 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
H A Dmhal_dip.c778 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in HAL_XC_DIP_Init()
779 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_Init()
1421 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux, CKG_IDCLK3_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_mux.c592 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux << 2, CKG_IDCLK3_MASK); in Hal_SC_mux_set_dipwin_ip_mux()
930 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in Hal_SC_EnableCLK_for_DIP()
931 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
936 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_INVERT); // Not Invert in Hal_SC_EnableCLK_for_DIP()
937 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
H A Dmhal_dip.c1142 … MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in HAL_XC_DIP_Init()
1143 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_Init()
1890 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux, CKG_IDCLK3_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_mux.c592 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux << 2, CKG_IDCLK3_MASK); in Hal_SC_mux_set_dipwin_ip_mux()
930 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in Hal_SC_EnableCLK_for_DIP()
931 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
936 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_INVERT); // Not Invert in Hal_SC_EnableCLK_for_DIP()
937 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
H A Dmhal_dip.c1142 … MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in HAL_XC_DIP_Init()
1143 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_Init()
1890 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux, CKG_IDCLK3_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_mux.c592 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux << 2, CKG_IDCLK3_MASK); in Hal_SC_mux_set_dipwin_ip_mux()
930 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in Hal_SC_EnableCLK_for_DIP()
931 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
936 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_INVERT); // Not Invert in Hal_SC_EnableCLK_for_DIP()
937 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
H A Dmhal_dip.c1141 … MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in HAL_XC_DIP_Init()
1142 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Di… in HAL_XC_DIP_Init()
1284 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
1444 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Di… in HAL_XC_DIP_ClearIntr()
1554 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_CpatureOneFrame2()
1924 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux, CKG_IDCLK3_MASK); in HAL_XC_DIP_SetMux()
3299 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Di… in HAL_XC_DIP_InterruptDetach()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_mux.c592 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux << 2, CKG_IDCLK3_MASK); in Hal_SC_mux_set_dipwin_ip_mux()
930 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in Hal_SC_EnableCLK_for_DIP()
931 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
936 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_INVERT); // Not Invert in Hal_SC_EnableCLK_for_DIP()
937 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
H A Dmhal_dip.c1142 … MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in HAL_XC_DIP_Init()
1143 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Di… in HAL_XC_DIP_Init()
1285 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
1445 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Di… in HAL_XC_DIP_ClearIntr()
1555 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_CpatureOneFrame2()
1925 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux, CKG_IDCLK3_MASK); in HAL_XC_DIP_SetMux()
3301 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Di… in HAL_XC_DIP_InterruptDetach()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_mux.c592 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux << 2, CKG_IDCLK3_MASK); in Hal_SC_mux_set_dipwin_ip_mux()
918 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in Hal_SC_EnableCLK_for_DIP()
919 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
924 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_INVERT); // Not Invert in Hal_SC_EnableCLK_for_DIP()
925 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
H A Dmhal_dip.c623 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in HAL_XC_DIP_Init()
624 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_Init()
1275 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux, CKG_IDCLK3_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_mux.c592 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux << 2, CKG_IDCLK3_MASK); in Hal_SC_mux_set_dipwin_ip_mux()
928 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in Hal_SC_EnableCLK_for_DIP()
929 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
934 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_INVERT); // Not Invert in Hal_SC_EnableCLK_for_DIP()
935 … MDrv_WriteRegBit(REG_CKG_IDCLK3, ENABLE, CKG_IDCLK3_GATED); // Enable clock in Hal_SC_EnableCLK_for_DIP()
H A Dmhal_dip.c656 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in HAL_XC_DIP_Init()
657 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_Init()
1310 MDrv_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux, CKG_IDCLK3_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_dip.c454 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in HAL_XC_DIP_Init()
455 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_Init()
1003 W2BYTEMSK( REG_CKG_IDCLK3, u16Clk_Mux ,CKG_IDCLK3_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_dip.c473 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in HAL_XC_DIP_Init()
474 … MDrv_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_Init()
1022 W2BYTEMSK( REG_CKG_IDCLK3, u16Clk_Mux ,CKG_IDCLK3_MASK); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/
H A Dmhal_xc_chip_config.h589 #define REG_CKG_IDCLK3 (REG_CLKGEN0_BASE + (0x59<<1) ) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/
H A Dmhal_xc_chip_config.h589 #define REG_CKG_IDCLK3 (REG_CLKGEN0_BASE + (0x59<<1) ) macro

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