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Searched refs:REG_BANK_DLC (Results 1 – 25 of 57) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/dlc/hal/k6/dlc/include/
H A DMsDlc_LIB_Group_DTV2.h128 #define REG_BANK_DLC 0x1A macro
134 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x)
135 #define H_BK_DLC(x) BK_REG_H((REG_BANK_DLC << 8),x)
227 … msWriteByte(BK_SCALER_BASE, REG_BANK_DLC);// for register bank switch...
/utopia/UTPA2-700.0.x/modules/dlc/hal/curry/dlc/include/
H A DMsDlc_LIB_Group_DTV2.h128 #define REG_BANK_DLC 0x1A macro
134 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x)
135 #define H_BK_DLC(x) BK_REG_H((REG_BANK_DLC << 8),x)
227 … msWriteByte(BK_SCALER_BASE, REG_BANK_DLC);// for register bank switch...
H A DMsDBC_LIB_Group_DTV2.h128 #define REG_BANK_DLC 0x1A macro
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
/utopia/UTPA2-700.0.x/modules/dlc/hal/kano/dlc/include/
H A DMsDlc_LIB_Group_DTV2.h128 #define REG_BANK_DLC 0x1A macro
134 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x)
135 #define H_BK_DLC(x) BK_REG_H((REG_BANK_DLC << 8),x)
227 … msWriteByte(BK_SCALER_BASE, REG_BANK_DLC);// for register bank switch...
H A DMsDBC_LIB_Group_DTV2.h128 #define REG_BANK_DLC 0x1A macro
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
/utopia/UTPA2-700.0.x/modules/dlc/hal/k6lite/dlc/include/
H A DMsDlc_LIB_Group_DTV2.h128 #define REG_BANK_DLC 0x1A macro
134 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x)
135 #define H_BK_DLC(x) BK_REG_H((REG_BANK_DLC << 8),x)
227 … msWriteByte(BK_SCALER_BASE, REG_BANK_DLC);// for register bank switch...
/utopia/UTPA2-700.0.x/modules/dlc/hal/maldives/dlc/include/
H A DMsDlc_LIB_Group_DTV3.h125 #define REG_BANK_DLC 0x1A macro
132 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x)
133 #define H_BK_DLC(x) BK_REG_H((REG_BANK_DLC << 8),x)
231 … msWriteByte(BK_SCALER_BASE, REG_BANK_DLC);// for register bank switch...
H A DMsDBC_LIB_Group_DTV2.h128 #define REG_BANK_DLC 0x1A macro
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
/utopia/UTPA2-700.0.x/modules/dlc/hal/mustang/dlc/include/
H A DMsDlc_LIB_Group_DTV3.h125 #define REG_BANK_DLC 0x1A macro
132 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x)
133 #define H_BK_DLC(x) BK_REG_H((REG_BANK_DLC << 8),x)
231 … msWriteByte(BK_SCALER_BASE, REG_BANK_DLC);// for register bank switch...
H A DMsDBC_LIB_Group_DTV2.h128 #define REG_BANK_DLC 0x1A macro
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
/utopia/UTPA2-700.0.x/modules/dlc/hal/maxim/dlc/include/
H A DMsDlc_LIB_Group_DTV3.h126 #define REG_BANK_DLC 0x1A macro
134 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x)
135 #define H_BK_DLC(x) BK_REG_H((REG_BANK_DLC << 8),x)
234 … msWriteByte(BK_SCALER_BASE, REG_BANK_DLC);// for register bank switch...
H A DMsDBC_LIB_Group_DTV2.h128 #define REG_BANK_DLC 0x1A macro
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
/utopia/UTPA2-700.0.x/modules/dlc/hal/macan/dlc/include/
H A DMsDlc_LIB_Group_DTV3.h126 #define REG_BANK_DLC 0x1A macro
134 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x)
135 #define H_BK_DLC(x) BK_REG_H((REG_BANK_DLC << 8),x)
234 … msWriteByte(BK_SCALER_BASE, REG_BANK_DLC);// for register bank switch...
H A DMsDBC_LIB_Group_DTV2.h128 #define REG_BANK_DLC 0x1A macro
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
/utopia/UTPA2-700.0.x/modules/dlc/hal/mainz/dlc/include/
H A DMsDlc_LIB_Group_DTV3.h126 #define REG_BANK_DLC 0x1A macro
134 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x)
135 #define H_BK_DLC(x) BK_REG_H((REG_BANK_DLC << 8),x)
234 … msWriteByte(BK_SCALER_BASE, REG_BANK_DLC);// for register bank switch...
H A DMsDBC_LIB_Group_DTV2.h128 #define REG_BANK_DLC 0x1A macro
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
/utopia/UTPA2-700.0.x/modules/dlc/hal/mooney/dlc/include/
H A DMsDlc_LIB_Group_DTV3.h126 #define REG_BANK_DLC 0x1A macro
134 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x)
135 #define H_BK_DLC(x) BK_REG_H((REG_BANK_DLC << 8),x)
234 … msWriteByte(BK_SCALER_BASE, REG_BANK_DLC);// for register bank switch...
H A DMsDBC_LIB_Group_DTV2.h128 #define REG_BANK_DLC 0x1A macro
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
/utopia/UTPA2-700.0.x/modules/dlc/hal/messi/dlc/include/
H A DMsDlc_LIB_Group_DTV3.h126 #define REG_BANK_DLC 0x1A macro
134 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x)
135 #define H_BK_DLC(x) BK_REG_H((REG_BANK_DLC << 8),x)
234 … msWriteByte(BK_SCALER_BASE, REG_BANK_DLC);// for register bank switch...
/utopia/UTPA2-700.0.x/modules/dlc/hal/manhattan/dlc/include/
H A DMsDlc_LIB_Group_DTV3.h126 #define REG_BANK_DLC 0x1A macro
134 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x)
135 #define H_BK_DLC(x) BK_REG_H((REG_BANK_DLC << 8),x)
234 … msWriteByte(BK_SCALER_BASE, REG_BANK_DLC);// for register bank switch...
H A DMsDBC_LIB_Group_DTV2.h128 #define REG_BANK_DLC 0x1A macro
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
/utopia/UTPA2-700.0.x/modules/dlc/hal/M7621/dlc/include/
H A DMsDlc_LIB_Group_DTV3.h126 #define REG_BANK_DLC 0x1A macro
134 #define L_BK_DLC(x) BK_REG_L((REG_BANK_DLC << 8),x)
135 #define H_BK_DLC(x) BK_REG_H((REG_BANK_DLC << 8),x)
234 … msWriteByte(BK_SCALER_BASE, REG_BANK_DLC);// for register bank switch...
H A DMsDBC_LIB_Group_DTV2.h128 #define REG_BANK_DLC 0x1A macro
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
/utopia/UTPA2-700.0.x/modules/dlc/hal/maserati/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h128 #define REG_BANK_DLC 0x1A macro
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...
/utopia/UTPA2-700.0.x/modules/dlc/hal/M7821/dlc/include/
H A DMsDBC_LIB_Group_DTV2.h128 #define REG_BANK_DLC 0x1A macro
164 … msWriteByte(SC1_REG_BASE, REG_BANK_DLC);// for register bank switch...

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