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Searched refs:MDrv_MFC_WriteRegsTbl (Results 1 – 25 of 48) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/mfc/hal/maxim/mfc/
H A Dmdrv_mfc_film.c595 MDrv_MFC_WriteRegsTbl(0x2900, tInitializeMfc_Common); in MDrv_MFC_InitializeMfc()
596 MDrv_MFC_WriteRegsTbl(0x2600, tInitializeMfc26_Common); in MDrv_MFC_InitializeMfc()
597 MDrv_MFC_WriteRegsTbl(0x2C00, tInitializeMFC2C); in MDrv_MFC_InitializeMfc()
600 MDrv_MFC_WriteRegsTbl(0x2900, tInitializeMfc_U02); in MDrv_MFC_InitializeMfc()
601 MDrv_MFC_WriteRegsTbl(0x2600, tInitializeMfc26_U02); in MDrv_MFC_InitializeMfc()
605 MDrv_MFC_WriteRegsTbl(0x2900, tInitializeMfc_U01); in MDrv_MFC_InitializeMfc()
606 MDrv_MFC_WriteRegsTbl(0x2600, tInitializeMfc26_U01); in MDrv_MFC_InitializeMfc()
618 MDrv_MFC_WriteRegsTbl(0x2000, tInitializeFilmMode); // initialize all of bank in MDrv_MFC_InitializeFilmMode()
H A Dmdrv_mfc_panel.c620 MDrv_MFC_WriteRegsTbl(0x2200, tInitializeTcon22b_Comm); // initialize all of bank in msInitializeTcon()
621 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_Comm); // initialize all of bank in msInitializeTcon()
630 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b); //each panel in msInitializeTcon()
634 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_42); in msInitializeTcon()
638 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_47); in msInitializeTcon()
641 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_55); in msInitializeTcon()
646 MDrv_MFC_WriteRegsTbl(0x2200, tInitializeTcon22c); // initialize all of bank in msInitializeTcon()
647 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23c); // initialize all of bank in msInitializeTcon()
969 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop2); in MDrv_MFC_InitializeScTop2_Bypanel()
H A Dmdrv_mfc_scalerop.c969 MDrv_MFC_WriteRegsTbl(0x2F00, tInitializeDispTgen); // initialize all of bank in MDrv_MFC_InitializeDispTgen()
970 MDrv_MFC_WriteRegsTbl(0x2A00, tInitializeDispLpll); in MDrv_MFC_InitializeDispTgen()
1410 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop1); //j081014 in MDrv_MFC_InitializeScTop()
1413 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop2_Comm); in MDrv_MFC_InitializeScTop()
1417 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop2_GIP); in MDrv_MFC_InitializeScTop()
1419 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop3); in MDrv_MFC_InitializeScTop()
1421 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop4); in MDrv_MFC_InitializeScTop()
1426 MDrv_MFC_WriteRegsTbl(0x3200, tIniTconCommPreEmphasis); in MDrv_MFC_InitializeScTop()
1475 MDrv_MFC_WriteRegsTbl(0x3000, tInitializeFRC); // initialize all of bank in MDrv_MFC_InitializeOPMFC()
H A Dmdrv_mfc_fb.c703 MDrv_MFC_WriteRegsTbl(0x1200, tInitializeMiuU3_DDR2_12xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
704 MDrv_MFC_WriteRegsTbl(0x1300, tInitializeMiuU3_DDR2_13xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
713 MDrv_MFC_WriteRegsTbl(0x1200, tInitializeMiuU3_DDR3_12xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
722 MDrv_MFC_WriteRegsTbl(0x1300, tInitializeMiuU3_DDR3_13xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
/utopia/UTPA2-700.0.x/modules/mfc/hal/manhattan/mfc/
H A Dmdrv_mfc_film.c595 MDrv_MFC_WriteRegsTbl(0x2900, tInitializeMfc_Common); in MDrv_MFC_InitializeMfc()
596 MDrv_MFC_WriteRegsTbl(0x2600, tInitializeMfc26_Common); in MDrv_MFC_InitializeMfc()
597 MDrv_MFC_WriteRegsTbl(0x2C00, tInitializeMFC2C); in MDrv_MFC_InitializeMfc()
600 MDrv_MFC_WriteRegsTbl(0x2900, tInitializeMfc_U02); in MDrv_MFC_InitializeMfc()
601 MDrv_MFC_WriteRegsTbl(0x2600, tInitializeMfc26_U02); in MDrv_MFC_InitializeMfc()
605 MDrv_MFC_WriteRegsTbl(0x2900, tInitializeMfc_U01); in MDrv_MFC_InitializeMfc()
606 MDrv_MFC_WriteRegsTbl(0x2600, tInitializeMfc26_U01); in MDrv_MFC_InitializeMfc()
618 MDrv_MFC_WriteRegsTbl(0x2000, tInitializeFilmMode); // initialize all of bank in MDrv_MFC_InitializeFilmMode()
H A Dmdrv_mfc_panel.c620 MDrv_MFC_WriteRegsTbl(0x2200, tInitializeTcon22b_Comm); // initialize all of bank in msInitializeTcon()
621 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_Comm); // initialize all of bank in msInitializeTcon()
630 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b); //each panel in msInitializeTcon()
634 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_42); in msInitializeTcon()
638 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_47); in msInitializeTcon()
641 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_55); in msInitializeTcon()
646 MDrv_MFC_WriteRegsTbl(0x2200, tInitializeTcon22c); // initialize all of bank in msInitializeTcon()
647 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23c); // initialize all of bank in msInitializeTcon()
969 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop2); in MDrv_MFC_InitializeScTop2_Bypanel()
H A Dmdrv_mfc_scalerop.c969 MDrv_MFC_WriteRegsTbl(0x2F00, tInitializeDispTgen); // initialize all of bank in MDrv_MFC_InitializeDispTgen()
970 MDrv_MFC_WriteRegsTbl(0x2A00, tInitializeDispLpll); in MDrv_MFC_InitializeDispTgen()
1410 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop1); //j081014 in MDrv_MFC_InitializeScTop()
1413 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop2_Comm); in MDrv_MFC_InitializeScTop()
1417 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop2_GIP); in MDrv_MFC_InitializeScTop()
1419 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop3); in MDrv_MFC_InitializeScTop()
1421 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop4); in MDrv_MFC_InitializeScTop()
1426 MDrv_MFC_WriteRegsTbl(0x3200, tIniTconCommPreEmphasis); in MDrv_MFC_InitializeScTop()
1475 MDrv_MFC_WriteRegsTbl(0x3000, tInitializeFRC); // initialize all of bank in MDrv_MFC_InitializeOPMFC()
H A Dmdrv_mfc_fb.c703 MDrv_MFC_WriteRegsTbl(0x1200, tInitializeMiuU3_DDR2_12xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
704 MDrv_MFC_WriteRegsTbl(0x1300, tInitializeMiuU3_DDR2_13xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
713 MDrv_MFC_WriteRegsTbl(0x1200, tInitializeMiuU3_DDR3_12xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
722 MDrv_MFC_WriteRegsTbl(0x1300, tInitializeMiuU3_DDR3_13xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
/utopia/UTPA2-700.0.x/modules/mfc/hal/maserati/mfc/
H A Dmdrv_mfc_film.c595 MDrv_MFC_WriteRegsTbl(0x2900, tInitializeMfc_Common); in MDrv_MFC_InitializeMfc()
596 MDrv_MFC_WriteRegsTbl(0x2600, tInitializeMfc26_Common); in MDrv_MFC_InitializeMfc()
597 MDrv_MFC_WriteRegsTbl(0x2C00, tInitializeMFC2C); in MDrv_MFC_InitializeMfc()
600 MDrv_MFC_WriteRegsTbl(0x2900, tInitializeMfc_U02); in MDrv_MFC_InitializeMfc()
601 MDrv_MFC_WriteRegsTbl(0x2600, tInitializeMfc26_U02); in MDrv_MFC_InitializeMfc()
605 MDrv_MFC_WriteRegsTbl(0x2900, tInitializeMfc_U01); in MDrv_MFC_InitializeMfc()
606 MDrv_MFC_WriteRegsTbl(0x2600, tInitializeMfc26_U01); in MDrv_MFC_InitializeMfc()
618 MDrv_MFC_WriteRegsTbl(0x2000, tInitializeFilmMode); // initialize all of bank in MDrv_MFC_InitializeFilmMode()
H A Dmdrv_mfc_panel.c620 MDrv_MFC_WriteRegsTbl(0x2200, tInitializeTcon22b_Comm); // initialize all of bank in msInitializeTcon()
621 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_Comm); // initialize all of bank in msInitializeTcon()
630 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b); //each panel in msInitializeTcon()
634 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_42); in msInitializeTcon()
638 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_47); in msInitializeTcon()
641 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_55); in msInitializeTcon()
646 MDrv_MFC_WriteRegsTbl(0x2200, tInitializeTcon22c); // initialize all of bank in msInitializeTcon()
647 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23c); // initialize all of bank in msInitializeTcon()
969 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop2); in MDrv_MFC_InitializeScTop2_Bypanel()
H A Dmdrv_mfc_scalerop.c969 MDrv_MFC_WriteRegsTbl(0x2F00, tInitializeDispTgen); // initialize all of bank in MDrv_MFC_InitializeDispTgen()
970 MDrv_MFC_WriteRegsTbl(0x2A00, tInitializeDispLpll); in MDrv_MFC_InitializeDispTgen()
1410 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop1); //j081014 in MDrv_MFC_InitializeScTop()
1413 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop2_Comm); in MDrv_MFC_InitializeScTop()
1417 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop2_GIP); in MDrv_MFC_InitializeScTop()
1419 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop3); in MDrv_MFC_InitializeScTop()
1421 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop4); in MDrv_MFC_InitializeScTop()
1426 MDrv_MFC_WriteRegsTbl(0x3200, tIniTconCommPreEmphasis); in MDrv_MFC_InitializeScTop()
1475 MDrv_MFC_WriteRegsTbl(0x3000, tInitializeFRC); // initialize all of bank in MDrv_MFC_InitializeOPMFC()
H A Dmdrv_mfc_fb.c703 MDrv_MFC_WriteRegsTbl(0x1200, tInitializeMiuU3_DDR2_12xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
704 MDrv_MFC_WriteRegsTbl(0x1300, tInitializeMiuU3_DDR2_13xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
713 MDrv_MFC_WriteRegsTbl(0x1200, tInitializeMiuU3_DDR3_12xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
722 MDrv_MFC_WriteRegsTbl(0x1300, tInitializeMiuU3_DDR3_13xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
/utopia/UTPA2-700.0.x/modules/mfc/hal/M7621/mfc/
H A Dmdrv_mfc_film.c595 MDrv_MFC_WriteRegsTbl(0x2900, tInitializeMfc_Common); in MDrv_MFC_InitializeMfc()
596 MDrv_MFC_WriteRegsTbl(0x2600, tInitializeMfc26_Common); in MDrv_MFC_InitializeMfc()
597 MDrv_MFC_WriteRegsTbl(0x2C00, tInitializeMFC2C); in MDrv_MFC_InitializeMfc()
600 MDrv_MFC_WriteRegsTbl(0x2900, tInitializeMfc_U02); in MDrv_MFC_InitializeMfc()
601 MDrv_MFC_WriteRegsTbl(0x2600, tInitializeMfc26_U02); in MDrv_MFC_InitializeMfc()
605 MDrv_MFC_WriteRegsTbl(0x2900, tInitializeMfc_U01); in MDrv_MFC_InitializeMfc()
606 MDrv_MFC_WriteRegsTbl(0x2600, tInitializeMfc26_U01); in MDrv_MFC_InitializeMfc()
618 MDrv_MFC_WriteRegsTbl(0x2000, tInitializeFilmMode); // initialize all of bank in MDrv_MFC_InitializeFilmMode()
H A Dmdrv_mfc_panel.c620 MDrv_MFC_WriteRegsTbl(0x2200, tInitializeTcon22b_Comm); // initialize all of bank in msInitializeTcon()
621 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_Comm); // initialize all of bank in msInitializeTcon()
630 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b); //each panel in msInitializeTcon()
634 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_42); in msInitializeTcon()
638 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_47); in msInitializeTcon()
641 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_55); in msInitializeTcon()
646 MDrv_MFC_WriteRegsTbl(0x2200, tInitializeTcon22c); // initialize all of bank in msInitializeTcon()
647 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23c); // initialize all of bank in msInitializeTcon()
969 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop2); in MDrv_MFC_InitializeScTop2_Bypanel()
H A Dmdrv_mfc_scalerop.c969 MDrv_MFC_WriteRegsTbl(0x2F00, tInitializeDispTgen); // initialize all of bank in MDrv_MFC_InitializeDispTgen()
970 MDrv_MFC_WriteRegsTbl(0x2A00, tInitializeDispLpll); in MDrv_MFC_InitializeDispTgen()
1410 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop1); //j081014 in MDrv_MFC_InitializeScTop()
1413 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop2_Comm); in MDrv_MFC_InitializeScTop()
1417 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop2_GIP); in MDrv_MFC_InitializeScTop()
1419 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop3); in MDrv_MFC_InitializeScTop()
1421 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop4); in MDrv_MFC_InitializeScTop()
1426 MDrv_MFC_WriteRegsTbl(0x3200, tIniTconCommPreEmphasis); in MDrv_MFC_InitializeScTop()
1475 MDrv_MFC_WriteRegsTbl(0x3000, tInitializeFRC); // initialize all of bank in MDrv_MFC_InitializeOPMFC()
H A Dmdrv_mfc_fb.c703 MDrv_MFC_WriteRegsTbl(0x1200, tInitializeMiuU3_DDR2_12xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
704 MDrv_MFC_WriteRegsTbl(0x1300, tInitializeMiuU3_DDR2_13xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
713 MDrv_MFC_WriteRegsTbl(0x1200, tInitializeMiuU3_DDR3_12xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
722 MDrv_MFC_WriteRegsTbl(0x1300, tInitializeMiuU3_DDR3_13xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
/utopia/UTPA2-700.0.x/modules/mfc/hal/M7821/mfc/
H A Dmdrv_mfc_film.c595 MDrv_MFC_WriteRegsTbl(0x2900, tInitializeMfc_Common); in MDrv_MFC_InitializeMfc()
596 MDrv_MFC_WriteRegsTbl(0x2600, tInitializeMfc26_Common); in MDrv_MFC_InitializeMfc()
597 MDrv_MFC_WriteRegsTbl(0x2C00, tInitializeMFC2C); in MDrv_MFC_InitializeMfc()
600 MDrv_MFC_WriteRegsTbl(0x2900, tInitializeMfc_U02); in MDrv_MFC_InitializeMfc()
601 MDrv_MFC_WriteRegsTbl(0x2600, tInitializeMfc26_U02); in MDrv_MFC_InitializeMfc()
605 MDrv_MFC_WriteRegsTbl(0x2900, tInitializeMfc_U01); in MDrv_MFC_InitializeMfc()
606 MDrv_MFC_WriteRegsTbl(0x2600, tInitializeMfc26_U01); in MDrv_MFC_InitializeMfc()
618 MDrv_MFC_WriteRegsTbl(0x2000, tInitializeFilmMode); // initialize all of bank in MDrv_MFC_InitializeFilmMode()
H A Dmdrv_mfc_panel.c620 MDrv_MFC_WriteRegsTbl(0x2200, tInitializeTcon22b_Comm); // initialize all of bank in msInitializeTcon()
621 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_Comm); // initialize all of bank in msInitializeTcon()
630 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b); //each panel in msInitializeTcon()
634 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_42); in msInitializeTcon()
638 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_47); in msInitializeTcon()
641 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_55); in msInitializeTcon()
646 MDrv_MFC_WriteRegsTbl(0x2200, tInitializeTcon22c); // initialize all of bank in msInitializeTcon()
647 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23c); // initialize all of bank in msInitializeTcon()
969 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop2); in MDrv_MFC_InitializeScTop2_Bypanel()
H A Dmdrv_mfc_scalerop.c969 MDrv_MFC_WriteRegsTbl(0x2F00, tInitializeDispTgen); // initialize all of bank in MDrv_MFC_InitializeDispTgen()
970 MDrv_MFC_WriteRegsTbl(0x2A00, tInitializeDispLpll); in MDrv_MFC_InitializeDispTgen()
1410 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop1); //j081014 in MDrv_MFC_InitializeScTop()
1413 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop2_Comm); in MDrv_MFC_InitializeScTop()
1417 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop2_GIP); in MDrv_MFC_InitializeScTop()
1419 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop3); in MDrv_MFC_InitializeScTop()
1421 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop4); in MDrv_MFC_InitializeScTop()
1426 MDrv_MFC_WriteRegsTbl(0x3200, tIniTconCommPreEmphasis); in MDrv_MFC_InitializeScTop()
1475 MDrv_MFC_WriteRegsTbl(0x3000, tInitializeFRC); // initialize all of bank in MDrv_MFC_InitializeOPMFC()
H A Dmdrv_mfc_fb.c703 MDrv_MFC_WriteRegsTbl(0x1200, tInitializeMiuU3_DDR2_12xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
704 MDrv_MFC_WriteRegsTbl(0x1300, tInitializeMiuU3_DDR2_13xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
713 MDrv_MFC_WriteRegsTbl(0x1200, tInitializeMiuU3_DDR3_12xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
722 MDrv_MFC_WriteRegsTbl(0x1300, tInitializeMiuU3_DDR3_13xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
/utopia/UTPA2-700.0.x/modules/mfc/hal/macan/mfc/
H A Dmdrv_mfc_film.c595 MDrv_MFC_WriteRegsTbl(0x2900, tInitializeMfc_Common); in MDrv_MFC_InitializeMfc()
596 MDrv_MFC_WriteRegsTbl(0x2600, tInitializeMfc26_Common); in MDrv_MFC_InitializeMfc()
597 MDrv_MFC_WriteRegsTbl(0x2C00, tInitializeMFC2C); in MDrv_MFC_InitializeMfc()
600 MDrv_MFC_WriteRegsTbl(0x2900, tInitializeMfc_U02); in MDrv_MFC_InitializeMfc()
601 MDrv_MFC_WriteRegsTbl(0x2600, tInitializeMfc26_U02); in MDrv_MFC_InitializeMfc()
605 MDrv_MFC_WriteRegsTbl(0x2900, tInitializeMfc_U01); in MDrv_MFC_InitializeMfc()
606 MDrv_MFC_WriteRegsTbl(0x2600, tInitializeMfc26_U01); in MDrv_MFC_InitializeMfc()
618 MDrv_MFC_WriteRegsTbl(0x2000, tInitializeFilmMode); // initialize all of bank in MDrv_MFC_InitializeFilmMode()
H A Dmdrv_mfc_panel.c620 MDrv_MFC_WriteRegsTbl(0x2200, tInitializeTcon22b_Comm); // initialize all of bank in msInitializeTcon()
621 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_Comm); // initialize all of bank in msInitializeTcon()
630 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b); //each panel in msInitializeTcon()
634 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_42); in msInitializeTcon()
638 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_47); in msInitializeTcon()
641 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23b_55); in msInitializeTcon()
646 MDrv_MFC_WriteRegsTbl(0x2200, tInitializeTcon22c); // initialize all of bank in msInitializeTcon()
647 MDrv_MFC_WriteRegsTbl(0x2300, tInitializeTcon23c); // initialize all of bank in msInitializeTcon()
969 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop2); in MDrv_MFC_InitializeScTop2_Bypanel()
H A Dmdrv_mfc_scalerop.c969 MDrv_MFC_WriteRegsTbl(0x2F00, tInitializeDispTgen); // initialize all of bank in MDrv_MFC_InitializeDispTgen()
970 MDrv_MFC_WriteRegsTbl(0x2A00, tInitializeDispLpll); in MDrv_MFC_InitializeDispTgen()
1410 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop1); //j081014 in MDrv_MFC_InitializeScTop()
1413 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop2_Comm); in MDrv_MFC_InitializeScTop()
1417 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop2_GIP); in MDrv_MFC_InitializeScTop()
1419 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop3); in MDrv_MFC_InitializeScTop()
1421 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop4); in MDrv_MFC_InitializeScTop()
1426 MDrv_MFC_WriteRegsTbl(0x3200, tIniTconCommPreEmphasis); in MDrv_MFC_InitializeScTop()
1475 MDrv_MFC_WriteRegsTbl(0x3000, tInitializeFRC); // initialize all of bank in MDrv_MFC_InitializeOPMFC()
H A Dmdrv_mfc_fb.c703 MDrv_MFC_WriteRegsTbl(0x1200, tInitializeMiuU3_DDR2_12xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
704 MDrv_MFC_WriteRegsTbl(0x1300, tInitializeMiuU3_DDR2_13xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
713 MDrv_MFC_WriteRegsTbl(0x1200, tInitializeMiuU3_DDR3_12xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
722 MDrv_MFC_WriteRegsTbl(0x1300, tInitializeMiuU3_DDR3_13xx); // initialize all of bank in MDrv_MFC_InitializeMiu()
H A Dmdrv_mfc_scalerip.c494 MDrv_MFC_WriteRegsTbl(0x2000, tInitializeIP); // initialize all of bank in MDrv_MFC_InitializeIP()
525 MDrv_MFC_WriteRegsTbl(0x2100, tInitializeOPM); // initialize all of bank in MDrv_MFC_InitializeOPM()
582 MDrv_MFC_WriteRegsTbl(0x2E00, tInitializeSnr); // initialize all of bank in MDrv_MFC_InitializeScaler()

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