| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_dip.c | 288 #define MDrv_DIP_WriteRegBit(u32Reg,bEnable,u8Mask)\ macro
1141 … MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in HAL_XC_DIP_Init()
1142 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Di… in HAL_XC_DIP_Init()
1187 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_INVERT); // Not Invert in HAL_XC_DIP_Init()
1188 …MDrv_DIP_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disable … in HAL_XC_DIP_Init()
1228 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_INVERT); // Not Invert in HAL_XC_DIP_Init()
1229 …MDrv_DIP_WriteRegBit(REG_CKG_PDW1, CKG_PDW1_GATED, CKG_PDW1_GATED); // Disable … in HAL_XC_DIP_Init()
1284 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
1292 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
1300 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
[all …]
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_dip.c | 289 #define MDrv_DIP_WriteRegBit(u32Reg,bEnable,u8Mask)\ macro
1142 … MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in HAL_XC_DIP_Init()
1143 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Di… in HAL_XC_DIP_Init()
1188 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_INVERT); // Not Invert in HAL_XC_DIP_Init()
1189 …MDrv_DIP_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disable … in HAL_XC_DIP_Init()
1229 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_INVERT); // Not Invert in HAL_XC_DIP_Init()
1230 …MDrv_DIP_WriteRegBit(REG_CKG_PDW1, CKG_PDW1_GATED, CKG_PDW1_GATED); // Disable … in HAL_XC_DIP_Init()
1285 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
1293 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
1301 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
[all …]
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_dip.c | 384 #define MDrv_DIP_WriteRegBit(u32Reg,bEnable,u8Mask)\ macro
1381 …MDrv_DIP_WriteRegBit(REG_CKG_DIP_FCLK, DISABLE, CKG_DIP_FCLK_GATED); // Enable … in HAL_XC_DIP_Init()
1411 … MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in HAL_XC_DIP_Init()
1412 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Dis… in HAL_XC_DIP_Init()
1470 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_INVERT); // Not Invert in HAL_XC_DIP_Init()
1471 …MDrv_DIP_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disab… in HAL_XC_DIP_Init()
1550 MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); in HAL_XC_DIP_EnableCaptureStream()
1559 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
1568 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_EnableCaptureStream()
1837 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_CpatureOneFrame2()
[all …]
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_dip.c | 289 #define MDrv_DIP_WriteRegBit(u32Reg,bEnable,u8Mask)\ macro
1142 … MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in HAL_XC_DIP_Init()
1143 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_Init()
1188 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_INVERT); // Not Invert in HAL_XC_DIP_Init()
1189 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_Init()
1229 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_INVERT); // Not Invert in HAL_XC_DIP_Init()
1230 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_Init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_dip.c | 289 #define MDrv_DIP_WriteRegBit(u32Reg,bEnable,u8Mask)\ macro
1142 … MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in HAL_XC_DIP_Init()
1143 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_Init()
1188 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_INVERT); // Not Invert in HAL_XC_DIP_Init()
1189 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_Init()
1229 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_INVERT); // Not Invert in HAL_XC_DIP_Init()
1230 … MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock in HAL_XC_DIP_Init()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_dip.c | 367 #define MDrv_DIP_WriteRegBit(u32Reg,bEnable,u8Mask)\ macro
1329 …MDrv_DIP_WriteRegBit(REG_CKG_DIP_FCLK, DISABLE, CKG_DIP_FCLK_GATED); // Enable … in HAL_XC_DIP_Init()
1359 … MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert in HAL_XC_DIP_Init()
1360 …MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock in HAL_XC_DIP_Init()
1417 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_INVERT); // Not Invert in HAL_XC_DIP_Init()
1418 … MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock in HAL_XC_DIP_Init()
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