| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_dip.c | 272 #define MDrv_DIP_WriteByteMask(u32Reg,u8Val,u8Msk)\ macro
1923 MDrv_DIP_WriteByteMask(REG_IPMUX_02_L, u8Data_Mux << 4, 0xF0); in HAL_XC_DIP_SetMux()
1924 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux, CKG_IDCLK3_MASK); in HAL_XC_DIP_SetMux()
1929 MDrv_DIP_WriteByteMask(REG_CKG_PDW0, u8Clk_Mux, CKG_PDW0_MASK); in HAL_XC_DIP_SetMux()
1934 MDrv_DIP_WriteByteMask(REG_CKG_PDW1, u8Clk_Mux, CKG_PDW1_MASK); in HAL_XC_DIP_SetMux()
3130 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
3131 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
3132 MDrv_DIP_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_128, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
3136 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
3137 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_256, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_dip.c | 273 #define MDrv_DIP_WriteByteMask(u32Reg,u8Val,u8Msk)\ macro
1889 MDrv_DIP_WriteByteMask(REG_IPMUX_02_L, u8Data_Mux << 4, 0xF0); in HAL_XC_DIP_SetMux()
1890 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux, CKG_IDCLK3_MASK); in HAL_XC_DIP_SetMux()
1895 MDrv_DIP_WriteByteMask(REG_CKG_PDW0, u8Clk_Mux, CKG_PDW0_MASK); in HAL_XC_DIP_SetMux()
1900 MDrv_DIP_WriteByteMask(REG_CKG_PDW1, u8Clk_Mux, CKG_PDW1_MASK); in HAL_XC_DIP_SetMux()
3081 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
3082 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
3083 MDrv_DIP_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_128, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
3087 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
3088 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_256, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_dip.c | 273 #define MDrv_DIP_WriteByteMask(u32Reg,u8Val,u8Msk)\ macro
1924 MDrv_DIP_WriteByteMask(REG_IPMUX_02_L, u8Data_Mux << 4, 0xF0); in HAL_XC_DIP_SetMux()
1925 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux, CKG_IDCLK3_MASK); in HAL_XC_DIP_SetMux()
1930 MDrv_DIP_WriteByteMask(REG_CKG_PDW0, u8Clk_Mux, CKG_PDW0_MASK); in HAL_XC_DIP_SetMux()
1935 MDrv_DIP_WriteByteMask(REG_CKG_PDW1, u8Clk_Mux, CKG_PDW1_MASK); in HAL_XC_DIP_SetMux()
3132 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
3133 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
3134 MDrv_DIP_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_128, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
3138 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
3139 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_256, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_dip.c | 273 #define MDrv_DIP_WriteByteMask(u32Reg,u8Val,u8Msk)\ macro
1889 MDrv_DIP_WriteByteMask(REG_IPMUX_02_L, u8Data_Mux << 4, 0xF0); in HAL_XC_DIP_SetMux()
1890 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux, CKG_IDCLK3_MASK); in HAL_XC_DIP_SetMux()
1895 MDrv_DIP_WriteByteMask(REG_CKG_PDW0, u8Clk_Mux, CKG_PDW0_MASK); in HAL_XC_DIP_SetMux()
1900 MDrv_DIP_WriteByteMask(REG_CKG_PDW1, u8Clk_Mux, CKG_PDW1_MASK); in HAL_XC_DIP_SetMux()
3085 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
3086 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
3087 MDrv_DIP_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_128, CKG_SC_ROT_MASK); in HAL_XC_DIP_Rotation()
3091 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED); in HAL_XC_DIP_Rotation()
3092 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_256, CKG_FMCLK_MASK); in HAL_XC_DIP_Rotation()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_dip.c | 351 #define MDrv_DIP_WriteByteMask(u32Reg,u8Val,u8Msk)\ macro
1330 …MDrv_DIP_WriteByteMask(REG_CKG_DIP_FCLK, CKG_DIP_FCLK_192MHZ, CKG_DIP_FCLK_MASK); // Selec… in HAL_XC_DIP_Init()
1529 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK0, CKG_FCLK_170MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
1535 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK0, CKG_FCLK_170MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
1593 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK0, CKG_FCLK_170MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
1601 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK0, CKG_FCLK_170MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
2042 MDrv_DIP_WriteByteMask(REG_IPMUX_02_L, u8Data_Mux << 4, 0xF0); in HAL_XC_DIP_SetMux()
2043 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux, CKG_IDCLK3_MASK); in HAL_XC_DIP_SetMux()
2048 MDrv_DIP_WriteByteMask(REG_CKG_PDW0, u8Clk_Mux, CKG_PDW0_MASK); in HAL_XC_DIP_SetMux()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_dip.c | 368 #define MDrv_DIP_WriteByteMask(u32Reg,u8Val,u8Msk)\ macro
1382 MDrv_DIP_WriteByteMask(REG_CKG_DIP_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_Init()
1607 MDrv_DIP_WriteByteMask(REG_CKG_DIP_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
1613 MDrv_DIP_WriteByteMask(REG_CKG_DIP_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
1671 MDrv_DIP_WriteByteMask(REG_CKG_DIP_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
1679 MDrv_DIP_WriteByteMask(REG_CKG_DIP_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK); in HAL_XC_DIP_EnableCaptureStream()
2161 MDrv_DIP_WriteByteMask(REG_IPMUX_02_L, u8Data_Mux << 4, 0xF0); in HAL_XC_DIP_SetMux()
2162 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux, CKG_IDCLK3_MASK); in HAL_XC_DIP_SetMux()
2167 MDrv_DIP_WriteByteMask(REG_CKG_PDW0, u8Clk_Mux, CKG_PDW0_MASK); in HAL_XC_DIP_SetMux()
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