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Searched refs:ISP_SPI_CMD_RDSR (Results 1 – 25 of 30) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/flash/hal/maldives/flash/serial/
H A DhalSERFLASH.c1649 ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR in _HAL_SERFLASH_WaitWriteDone()
1688 ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR in _HAL_SERFLASH_CheckWriteDone()
3830 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR); // RDSR in HAL_SERFLASH_ReadStatusReg()
4546 _HAL_FSP_SetCommand(ISP_SPI_CMD_RDSR); in _HAL_FSP_CheckRDSR()
4635 HAL_WriteByte((REG_FSP_WRITE_BUFF + 3),ISP_SPI_CMD_RDSR); in _HAL_FSP_PROGRAM_SPSR()
4698 HAL_WriteByte((REG_FSP_WRITE_BUFF + 4),ISP_SPI_CMD_RDSR); in _HAL_FSP_BlockErase()
4700 HAL_WriteByte((REG_FSP_WRITE_BUFF + 5),ISP_SPI_CMD_RDSR); in _HAL_FSP_BlockErase()
4759 HAL_WriteByte((REG_FSP_WRITE_BUFF + 9),ISP_SPI_CMD_RDSR); in HAL_FSP_Write()
H A DregSERFLASH.h151 #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) macro
/utopia/UTPA2-700.0.x/modules/flash/hal/manhattan/flash/serial/
H A DregSERFLASH.h153 #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) macro
H A DhalSERFLASH.c1552 ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR in _HAL_SERFLASH_WaitWriteDone()
1592 ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR in _HAL_SERFLASH_CheckWriteDone()
3669 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR); // RDSR in HAL_SERFLASH_ReadStatusReg()
/utopia/UTPA2-700.0.x/modules/flash/hal/macan/flash/serial/
H A DregSERFLASH.h153 #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) macro
H A DhalSERFLASH.c1514 ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR in _HAL_SERFLASH_WaitWriteDone()
1554 ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR in _HAL_SERFLASH_CheckWriteDone()
3631 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR); // RDSR in HAL_SERFLASH_ReadStatusReg()
/utopia/UTPA2-700.0.x/modules/flash/hal/messi/flash/serial/
H A DregSERFLASH.h154 #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) macro
H A DhalSERFLASH.c1522 ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR in _HAL_SERFLASH_WaitWriteDone()
1562 ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR in _HAL_SERFLASH_CheckWriteDone()
3641 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR); // RDSR in HAL_SERFLASH_ReadStatusReg()
/utopia/UTPA2-700.0.x/modules/flash/hal/maxim/flash/serial/
H A DregSERFLASH.h153 #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) macro
H A DhalSERFLASH.c1551 ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR in _HAL_SERFLASH_WaitWriteDone()
1591 ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR in _HAL_SERFLASH_CheckWriteDone()
3668 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR); // RDSR in HAL_SERFLASH_ReadStatusReg()
/utopia/UTPA2-700.0.x/modules/flash/hal/maserati/flash/serial/
H A DregSERFLASH.h153 #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) macro
H A DhalSERFLASH.c1551 ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR in _HAL_SERFLASH_WaitWriteDone()
1591 ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR in _HAL_SERFLASH_CheckWriteDone()
3668 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR); // RDSR in HAL_SERFLASH_ReadStatusReg()
/utopia/UTPA2-700.0.x/modules/flash/hal/M7821/flash/serial/
H A DregSERFLASH.h153 #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) macro
H A DhalSERFLASH.c1551 ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR in _HAL_SERFLASH_WaitWriteDone()
1591 ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR in _HAL_SERFLASH_CheckWriteDone()
3668 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR); // RDSR in HAL_SERFLASH_ReadStatusReg()
/utopia/UTPA2-700.0.x/modules/flash/hal/M7621/flash/serial/
H A DregSERFLASH.h153 #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) macro
H A DhalSERFLASH.c1551 ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR in _HAL_SERFLASH_WaitWriteDone()
1591 ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR in _HAL_SERFLASH_CheckWriteDone()
3668 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR); // RDSR in HAL_SERFLASH_ReadStatusReg()
/utopia/UTPA2-700.0.x/modules/flash/hal/mainz/flash/serial/
H A DregSERFLASH.h154 #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) macro
H A DhalSERFLASH.c1522 ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR in _HAL_SERFLASH_WaitWriteDone()
1562 ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR in _HAL_SERFLASH_CheckWriteDone()
3641 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR); // RDSR in HAL_SERFLASH_ReadStatusReg()
/utopia/UTPA2-700.0.x/modules/flash/hal/mooney/flash/serial/
H A DregSERFLASH.h153 #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) macro
H A DhalSERFLASH.c1514 ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR in _HAL_SERFLASH_WaitWriteDone()
1554 ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR in _HAL_SERFLASH_CheckWriteDone()
3631 ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR); // RDSR in HAL_SERFLASH_ReadStatusReg()
/utopia/UTPA2-700.0.x/modules/flash/hal/k6lite/flash/serial/
H A DregSERFLASH.h153 #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) macro
/utopia/UTPA2-700.0.x/modules/flash/hal/kano/flash/serial/
H A DregSERFLASH.h153 #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) macro
/utopia/UTPA2-700.0.x/modules/flash/hal/curry/flash/serial/
H A DregSERFLASH.h153 #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) macro
/utopia/UTPA2-700.0.x/modules/flash/hal/k6/flash/serial/
H A DregSERFLASH.h153 #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) macro
/utopia/UTPA2-700.0.x/modules/flash/hal/mustang/flash/serial/
H A DregSERFLASH.h152 #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) macro

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