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Searched refs:H_BK_CLKGEN0 (Results 1 – 25 of 35) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vd/hal/mainz/avd/
H A DhalAVD.c2972 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
3030 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
3483 …RIU_WriteRegBit (H_BK_CLKGEN0(0x20), bEnable, BIT(0));// CLK_VD, 20090628 BY patch clock enable, T… in HAL_AVD_AFEC_SetClock()
3485 …RIU_WriteRegBit (H_BK_CLKGEN0(0x21), bEnable, BIT(0));// CLK_VD200, 20090628 BY patch clock enable… in HAL_AVD_AFEC_SetClock()
3486 …RIU_WriteByteMask(H_BK_CLKGEN0(0x21), 0x00<<2, BMASK(3:2)); // 20090628 BY put VD200 clock settin… in HAL_AVD_AFEC_SetClock()
3488 RIU_WriteByteMask (H_BK_CLKGEN0(0x22), 0x00, BMASK(3:0));// CLK_mailbox1 in HAL_AVD_AFEC_SetClock()
3490 RIU_WriteRegBit (H_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD32FSC in HAL_AVD_AFEC_SetClock()
/utopia/UTPA2-700.0.x/modules/vd/hal/mustang/avd/
H A DhalAVD.c6316 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6374 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6839 …RIU_WriteRegBit (H_BK_CLKGEN0(0x20), bEnable, BIT(0));// CLK_VD, 20090628 BY patch clock enable, T… in HAL_AVD_AFEC_SetClock()
6841 …RIU_WriteRegBit (H_BK_CLKGEN0(0x21), bEnable, BIT(0));// CLK_VD200, 20090628 BY patch clock enable… in HAL_AVD_AFEC_SetClock()
6842 …RIU_WriteByteMask(H_BK_CLKGEN0(0x21), 0x00<<2, BMASK(3:2)); // 20090628 BY put VD200 clock settin… in HAL_AVD_AFEC_SetClock()
6844 RIU_WriteByteMask (H_BK_CLKGEN0(0x22), 0x00, BMASK(3:0));// CLK_mailbox1 in HAL_AVD_AFEC_SetClock()
6846 RIU_WriteRegBit (H_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD32FSC in HAL_AVD_AFEC_SetClock()
H A DregAVD.h131 #define H_BK_CLKGEN0(x) BK_REG_H(CLKGEN0_REG_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/M7821/avd/
H A DhalAVD.c6331 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6395 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6927 …RIU_WriteRegBit (H_BK_CLKGEN0(0x20), bEnable, BIT(0));// CLK_VD, 20090628 BY patch clock enable, T… in HAL_AVD_AFEC_SetClock()
6946 …RIU_WriteRegBit (H_BK_CLKGEN0(0x21), bEnable, BIT(0));// CLK_VD200, 20090628 BY patch clock enable… in HAL_AVD_AFEC_SetClock()
6947 …RIU_WriteByteMask(H_BK_CLKGEN0(0x21), 0x00<<2, BMASK(3:2)); // 20090628 BY put VD200 clock settin… in HAL_AVD_AFEC_SetClock()
6949 RIU_WriteByteMask (H_BK_CLKGEN0(0x22), 0x00, BMASK(3:0));// CLK_mailbox1 in HAL_AVD_AFEC_SetClock()
6966 RIU_WriteRegBit (H_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD32FSC in HAL_AVD_AFEC_SetClock()
/utopia/UTPA2-700.0.x/modules/vd/hal/kano/avd/
H A DhalAVD.c6331 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6395 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6927 …RIU_WriteRegBit (H_BK_CLKGEN0(0x20), bEnable, BIT(0));// CLK_VD, 20090628 BY patch clock enable, T… in HAL_AVD_AFEC_SetClock()
6946 …RIU_WriteRegBit (H_BK_CLKGEN0(0x21), bEnable, BIT(0));// CLK_VD200, 20090628 BY patch clock enable… in HAL_AVD_AFEC_SetClock()
6947 …RIU_WriteByteMask(H_BK_CLKGEN0(0x21), 0x00<<2, BMASK(3:2)); // 20090628 BY put VD200 clock settin… in HAL_AVD_AFEC_SetClock()
6949 RIU_WriteByteMask (H_BK_CLKGEN0(0x22), 0x00, BMASK(3:0));// CLK_mailbox1 in HAL_AVD_AFEC_SetClock()
6966 RIU_WriteRegBit (H_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD32FSC in HAL_AVD_AFEC_SetClock()
H A DregAVD.h131 #define H_BK_CLKGEN0(x) BK_REG_H(CLKGEN0_REG_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/manhattan/avd/
H A DhalAVD.c6330 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6394 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6907 …RIU_WriteRegBit (H_BK_CLKGEN0(0x20), bEnable, BIT(0));// CLK_VD, 20090628 BY patch clock enable, T… in HAL_AVD_AFEC_SetClock()
6909 …RIU_WriteRegBit (H_BK_CLKGEN0(0x21), bEnable, BIT(0));// CLK_VD200, 20090628 BY patch clock enable… in HAL_AVD_AFEC_SetClock()
6910 …RIU_WriteByteMask(H_BK_CLKGEN0(0x21), 0x00<<2, BMASK(3:2)); // 20090628 BY put VD200 clock settin… in HAL_AVD_AFEC_SetClock()
6912 RIU_WriteByteMask (H_BK_CLKGEN0(0x22), 0x00, BMASK(3:0));// CLK_mailbox1 in HAL_AVD_AFEC_SetClock()
6914 RIU_WriteRegBit (H_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD32FSC in HAL_AVD_AFEC_SetClock()
/utopia/UTPA2-700.0.x/modules/vd/hal/M7621/avd/
H A DhalAVD.c6331 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6395 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6927 …RIU_WriteRegBit (H_BK_CLKGEN0(0x20), bEnable, BIT(0));// CLK_VD, 20090628 BY patch clock enable, T… in HAL_AVD_AFEC_SetClock()
6946 …RIU_WriteRegBit (H_BK_CLKGEN0(0x21), bEnable, BIT(0));// CLK_VD200, 20090628 BY patch clock enable… in HAL_AVD_AFEC_SetClock()
6947 …RIU_WriteByteMask(H_BK_CLKGEN0(0x21), 0x00<<2, BMASK(3:2)); // 20090628 BY put VD200 clock settin… in HAL_AVD_AFEC_SetClock()
6949 RIU_WriteByteMask (H_BK_CLKGEN0(0x22), 0x00, BMASK(3:0));// CLK_mailbox1 in HAL_AVD_AFEC_SetClock()
6966 RIU_WriteRegBit (H_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD32FSC in HAL_AVD_AFEC_SetClock()
/utopia/UTPA2-700.0.x/modules/vd/hal/maldives/avd/
H A DhalAVD.c6316 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6374 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6839 …RIU_WriteRegBit (H_BK_CLKGEN0(0x20), bEnable, BIT(0));// CLK_VD, 20090628 BY patch clock enable, T… in HAL_AVD_AFEC_SetClock()
6841 …RIU_WriteRegBit (H_BK_CLKGEN0(0x21), bEnable, BIT(0));// CLK_VD200, 20090628 BY patch clock enable… in HAL_AVD_AFEC_SetClock()
6842 …RIU_WriteByteMask(H_BK_CLKGEN0(0x21), 0x00<<2, BMASK(3:2)); // 20090628 BY put VD200 clock settin… in HAL_AVD_AFEC_SetClock()
6844 RIU_WriteByteMask (H_BK_CLKGEN0(0x22), 0x00, BMASK(3:0));// CLK_mailbox1 in HAL_AVD_AFEC_SetClock()
6846 RIU_WriteRegBit (H_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD32FSC in HAL_AVD_AFEC_SetClock()
/utopia/UTPA2-700.0.x/modules/vd/hal/messi/avd/
H A DhalAVD.c2972 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
3030 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
3483 …RIU_WriteRegBit (H_BK_CLKGEN0(0x20), bEnable, BIT(0));// CLK_VD, 20090628 BY patch clock enable, T… in HAL_AVD_AFEC_SetClock()
3485 …RIU_WriteRegBit (H_BK_CLKGEN0(0x21), bEnable, BIT(0));// CLK_VD200, 20090628 BY patch clock enable… in HAL_AVD_AFEC_SetClock()
3486 …RIU_WriteByteMask(H_BK_CLKGEN0(0x21), 0x00<<2, BMASK(3:2)); // 20090628 BY put VD200 clock settin… in HAL_AVD_AFEC_SetClock()
3488 RIU_WriteByteMask (H_BK_CLKGEN0(0x22), 0x00, BMASK(3:0));// CLK_mailbox1 in HAL_AVD_AFEC_SetClock()
3490 RIU_WriteRegBit (H_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD32FSC in HAL_AVD_AFEC_SetClock()
/utopia/UTPA2-700.0.x/modules/vd/hal/maserati/avd/
H A DhalAVD.c6331 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6395 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6927 …RIU_WriteRegBit (H_BK_CLKGEN0(0x20), bEnable, BIT(0));// CLK_VD, 20090628 BY patch clock enable, T… in HAL_AVD_AFEC_SetClock()
6946 …RIU_WriteRegBit (H_BK_CLKGEN0(0x21), bEnable, BIT(0));// CLK_VD200, 20090628 BY patch clock enable… in HAL_AVD_AFEC_SetClock()
6947 …RIU_WriteByteMask(H_BK_CLKGEN0(0x21), 0x00<<2, BMASK(3:2)); // 20090628 BY put VD200 clock settin… in HAL_AVD_AFEC_SetClock()
6949 RIU_WriteByteMask (H_BK_CLKGEN0(0x22), 0x00, BMASK(3:0));// CLK_mailbox1 in HAL_AVD_AFEC_SetClock()
6966 RIU_WriteRegBit (H_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD32FSC in HAL_AVD_AFEC_SetClock()
/utopia/UTPA2-700.0.x/modules/vd/hal/maxim/avd/
H A DhalAVD.c6331 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6395 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6927 …RIU_WriteRegBit (H_BK_CLKGEN0(0x20), bEnable, BIT(0));// CLK_VD, 20090628 BY patch clock enable, T… in HAL_AVD_AFEC_SetClock()
6946 …RIU_WriteRegBit (H_BK_CLKGEN0(0x21), bEnable, BIT(0));// CLK_VD200, 20090628 BY patch clock enable… in HAL_AVD_AFEC_SetClock()
6947 …RIU_WriteByteMask(H_BK_CLKGEN0(0x21), 0x00<<2, BMASK(3:2)); // 20090628 BY put VD200 clock settin… in HAL_AVD_AFEC_SetClock()
6949 RIU_WriteByteMask (H_BK_CLKGEN0(0x22), 0x00, BMASK(3:0));// CLK_mailbox1 in HAL_AVD_AFEC_SetClock()
6966 RIU_WriteRegBit (H_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD32FSC in HAL_AVD_AFEC_SetClock()
H A DregAVD.h131 #define H_BK_CLKGEN0(x) BK_REG_H(CLKGEN0_REG_BASE, x) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/mooney/avd/
H A DhalAVD.c2971 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
3029 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
3482 …RIU_WriteRegBit (H_BK_CLKGEN0(0x20), bEnable, BIT(0));// CLK_VD, 20090628 BY patch clock enable, T… in HAL_AVD_AFEC_SetClock()
3484 …RIU_WriteRegBit (H_BK_CLKGEN0(0x21), bEnable, BIT(0));// CLK_VD200, 20090628 BY patch clock enable… in HAL_AVD_AFEC_SetClock()
3485 …RIU_WriteByteMask(H_BK_CLKGEN0(0x21), 0x00<<2, BMASK(3:2)); // 20090628 BY put VD200 clock settin… in HAL_AVD_AFEC_SetClock()
3487 RIU_WriteByteMask (H_BK_CLKGEN0(0x22), 0x00, BMASK(3:0));// CLK_mailbox1 in HAL_AVD_AFEC_SetClock()
3489 RIU_WriteRegBit (H_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD32FSC in HAL_AVD_AFEC_SetClock()
/utopia/UTPA2-700.0.x/modules/vd/hal/macan/avd/
H A DhalAVD.c6318 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6376 …RIU_WriteByteMask(H_BK_CLKGEN0(0x22), 0x00<<2, BMASK(3:2)); // 20090628 BY put mailbo1 clock sett… in HAL_AVD_VDMCU_SetClock()
6855 …RIU_WriteRegBit (H_BK_CLKGEN0(0x20), bEnable, BIT(0));// CLK_VD, 20090628 BY patch clock enable, T… in HAL_AVD_AFEC_SetClock()
6857 …RIU_WriteRegBit (H_BK_CLKGEN0(0x21), bEnable, BIT(0));// CLK_VD200, 20090628 BY patch clock enable… in HAL_AVD_AFEC_SetClock()
6858 …RIU_WriteByteMask(H_BK_CLKGEN0(0x21), 0x00<<2, BMASK(3:2)); // 20090628 BY put VD200 clock settin… in HAL_AVD_AFEC_SetClock()
6860 RIU_WriteByteMask (H_BK_CLKGEN0(0x22), 0x00, BMASK(3:0));// CLK_mailbox1 in HAL_AVD_AFEC_SetClock()
6862 RIU_WriteRegBit (H_BK_CLKGEN0(0x23), bEnable, BIT(0));// CLK_VD32FSC in HAL_AVD_AFEC_SetClock()
/utopia/UTPA2-700.0.x/modules/ve/hal/mustang/ve/
H A Dmhal_tvencoder.c291 MDrv_WriteByteMask(H_BK_CLKGEN0(0x24), 0x08, 0x0f); // clock of vedac in Hal_VE_init()
949 MDrv_WriteByteMask(H_BK_CLKGEN0(0x24), !ben, 0x01); // clock of vedac Ena/disable in Hal_VE_set_clk_on_off()
/utopia/UTPA2-700.0.x/modules/ve/hal/maldives/ve/
H A Dmhal_tvencoder.c291 MDrv_WriteByteMask(H_BK_CLKGEN0(0x24), 0x08, 0x0f); // clock of vedac in Hal_VE_init()
947 MDrv_WriteByteMask(H_BK_CLKGEN0(0x24), !ben, 0x01); // clock of vedac Ena/disable in Hal_VE_set_clk_on_off()
/utopia/UTPA2-700.0.x/modules/ve/hal/mainz/ve/
H A Dmhal_tvencoder.c294 MDrv_WriteByteMask(H_BK_CLKGEN0(0x24), 0x08, 0x0f); // clock of vedac in Hal_VE_init()
965 MDrv_WriteByteMask(H_BK_CLKGEN0(0x24), !ben, 0x01); // clock of vedac Ena/disable in Hal_VE_set_clk_on_off()
/utopia/UTPA2-700.0.x/modules/ve/hal/messi/ve/
H A Dmhal_tvencoder.c294 MDrv_WriteByteMask(H_BK_CLKGEN0(0x24), 0x08, 0x0f); // clock of vedac in Hal_VE_init()
965 MDrv_WriteByteMask(H_BK_CLKGEN0(0x24), !ben, 0x01); // clock of vedac Ena/disable in Hal_VE_set_clk_on_off()
/utopia/UTPA2-700.0.x/modules/ve/hal/macan/ve/
H A Dmhal_tvencoder.c293 MDrv_WriteByteMask(H_BK_CLKGEN0(0x24), 0x08, 0x0f); // clock of vedac in Hal_VE_init()
969 MDrv_WriteByteMask(H_BK_CLKGEN0(0x24), !ben, 0x01); // clock of vedac Ena/disable in Hal_VE_set_clk_on_off()
/utopia/UTPA2-700.0.x/modules/ve/hal/maxim/ve/
H A Dmhal_tvencoder.c301 MDrv_WriteByteMask(H_BK_CLKGEN0(0x24), 0x08, 0x0f); // clock of vedac in Hal_VE_init()
1023 MDrv_WriteByteMask(H_BK_CLKGEN0(0x24), !ben, 0x01); // clock of vedac Ena/disable in Hal_VE_set_clk_on_off()
/utopia/UTPA2-700.0.x/modules/ve/hal/manhattan/ve/
H A Dmhal_tvencoder.c297 MDrv_WriteByteMask(H_BK_CLKGEN0(0x24), 0x08, 0x0f); // clock of vedac in Hal_VE_init()
971 MDrv_WriteByteMask(H_BK_CLKGEN0(0x24), !ben, 0x01); // clock of vedac Ena/disable in Hal_VE_set_clk_on_off()
/utopia/UTPA2-700.0.x/modules/ve/hal/maserati/ve/
H A Dmhal_tvencoder.c300 MDrv_WriteByteMask(H_BK_CLKGEN0(0x24), 0x08, 0x0f); // clock of vedac in Hal_VE_init()
1022 MDrv_WriteByteMask(H_BK_CLKGEN0(0x24), !ben, 0x01); // clock of vedac Ena/disable in Hal_VE_set_clk_on_off()
/utopia/UTPA2-700.0.x/modules/ve/hal/M7621/ve/
H A Dmhal_tvencoder.c301 MDrv_WriteByteMask(H_BK_CLKGEN0(0x24), 0x08, 0x0f); // clock of vedac in Hal_VE_init()
1023 MDrv_WriteByteMask(H_BK_CLKGEN0(0x24), !ben, 0x01); // clock of vedac Ena/disable in Hal_VE_set_clk_on_off()
/utopia/UTPA2-700.0.x/modules/ve/hal/M7821/ve/
H A Dmhal_tvencoder.c300 MDrv_WriteByteMask(H_BK_CLKGEN0(0x24), 0x08, 0x0f); // clock of vedac in Hal_VE_init()
1022 MDrv_WriteByteMask(H_BK_CLKGEN0(0x24), !ben, 0x01); // clock of vedac Ena/disable in Hal_VE_set_clk_on_off()

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