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Searched refs:EN_OUTPUT_TIMING_CHG_DCLK (Results 1 – 2 of 2) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/drv/xc/
H A Dmdrv_sc_display.c203 EN_OUTPUT_TIMING_CHG_DCLK = 0, enumerator
1630 if (u16UserStep > 1 && AdjustMode != EN_OUTPUT_TIMING_CHG_DCLK) in _MDrv_XC_SetHttVtt_Steply()
H A Dmdrv_sc_display.c.0203 EN_OUTPUT_TIMING_CHG_DCLK = 0,
1628 if (u16UserStep > 1 && AdjustMode != EN_OUTPUT_TIMING_CHG_DCLK)