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Searched refs:DWIN_W_LIMITE_OFT (Results 1 – 16 of 16) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_dip.c1795 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
1804 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
1813 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
1833 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
1842 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
1851 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_dip.c1775 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
1784 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
1793 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
1813 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
1822 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
1831 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_dip.c1870 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
1879 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
1888 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
1908 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
1917 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
1926 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_dip.c2050 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2059 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2068 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2088 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
2097 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
2106 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_dip.c2176 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2185 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2194 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2214 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
2223 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
2232 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_dip.c2178 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2187 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2196 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2216 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
2225 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
2234 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_dip.c1901 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
1915 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
1929 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
1955 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
1969 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
1983 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_dip.c1288 u32BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
1297 u32BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
1316 u32BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
1325 u32BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_dip.c1299 u32BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
1308 u32BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
1327 u32BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
1336 u32BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_dip.c2537 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2551 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2565 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2591 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
2605 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
2619 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_dip.c2492 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2506 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2520 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2546 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
2560 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
2574 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_dip.c2538 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2552 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2566 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2592 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
2606 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
2620 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_dip.c2492 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2506 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2520 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2546 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
2560 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
2574 u64_result|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_dip.c2738 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2747 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2767 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
2776 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/include/
H A Ddrv_sc_DIP_scaling.h108 #define DWIN_W_LIMITE_OFT 31UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_dip.c2933 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2942 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase0()
2962 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()
2971 u64BufEnd|=(1<<DWIN_W_LIMITE_OFT); in HAL_XC_DIP_SetBase1()