| /utopia/UTPA2-700.0.x/modules/vd/hal/mainz/avd/ |
| H A D | halAVD.c | 2727 _RV1(BK_AFEC_D8, 0x20),
3428 u8AfecD8=RIU_ReadByte(BK_AFEC_D8); in HAL_AVD_AFEC_McuReset()
3445 RIU_WriteByteMask (BK_AFEC_D8, u8AfecD8 & (~ BIT(3)), BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
4187 RIU_WriteByteMask (BK_AFEC_D8, u8Limit<< 4, BMASK(7:4)); in HAL_AVD_AFEC_SetSwingLimit()
4204 RIU_WriteByteMask( BK_AFEC_D8, BIT(3), BIT(3) ); // auto clear to 0 by dsp in HAL_AVD_AFEC_SetChannelChange()
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| H A D | regAVD.h | 365 #define BK_AFEC_D8 (AFEC_REG_BASE+0xD8) macro
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| /utopia/UTPA2-700.0.x/modules/vd/hal/mustang/avd/ |
| H A D | halAVD.c | 6071 _RV1(BK_AFEC_D8, 0x20),
6784 u8AfecD8=RIU_ReadByte(BK_AFEC_D8); in HAL_AVD_AFEC_McuReset()
6801 RIU_WriteByteMask (BK_AFEC_D8, u8AfecD8 & (~ BIT(3)), BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
7549 RIU_WriteByteMask (BK_AFEC_D8, u8Limit<< 4, BMASK(7:4)); in HAL_AVD_AFEC_SetSwingLimit()
7566 RIU_WriteByteMask( BK_AFEC_D8, BIT(3), BIT(3) ); // auto clear to 0 by dsp in HAL_AVD_AFEC_SetChannelChange()
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| H A D | regAVD.h | 365 #define BK_AFEC_D8 (AFEC_REG_BASE+0xD8) macro
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| /utopia/UTPA2-700.0.x/modules/vd/hal/M7821/avd/ |
| H A D | halAVD.c | 6079 _RV1(BK_AFEC_D8, 0x20),
6823 u8AfecD8=RIU_ReadByte(BK_AFEC_D8); in HAL_AVD_AFEC_McuReset()
6860 RIU_WriteByteMask (BK_AFEC_D8, u8AfecD8 & (~ BIT(3)), BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
7675 RIU_WriteByteMask (BK_AFEC_D8, u8Limit<< 4, BMASK(7:4)); in HAL_AVD_AFEC_SetSwingLimit()
7692 RIU_WriteByteMask( BK_AFEC_D8, BIT(3), BIT(3) ); // auto clear to 0 by dsp in HAL_AVD_AFEC_SetChannelChange()
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| H A D | regAVD.h | 365 #define BK_AFEC_D8 (AFEC_REG_BASE+0xD8) macro
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| /utopia/UTPA2-700.0.x/modules/vd/hal/kano/avd/ |
| H A D | halAVD.c | 6079 _RV1(BK_AFEC_D8, 0x20),
6823 u8AfecD8=RIU_ReadByte(BK_AFEC_D8); in HAL_AVD_AFEC_McuReset()
6860 RIU_WriteByteMask (BK_AFEC_D8, u8AfecD8 & (~ BIT(3)), BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
7675 RIU_WriteByteMask (BK_AFEC_D8, u8Limit<< 4, BMASK(7:4)); in HAL_AVD_AFEC_SetSwingLimit()
7692 RIU_WriteByteMask( BK_AFEC_D8, BIT(3), BIT(3) ); // auto clear to 0 by dsp in HAL_AVD_AFEC_SetChannelChange()
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| H A D | regAVD.h | 365 #define BK_AFEC_D8 (AFEC_REG_BASE+0xD8) macro
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| /utopia/UTPA2-700.0.x/modules/vd/hal/manhattan/avd/ |
| H A D | halAVD.c | 6078 _RV1(BK_AFEC_D8, 0x20),
6822 u8AfecD8=RIU_ReadByte(BK_AFEC_D8); in HAL_AVD_AFEC_McuReset()
6859 RIU_WriteByteMask (BK_AFEC_D8, u8AfecD8 & (~ BIT(3)), BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
7622 RIU_WriteByteMask (BK_AFEC_D8, u8Limit<< 4, BMASK(7:4)); in HAL_AVD_AFEC_SetSwingLimit()
7639 RIU_WriteByteMask( BK_AFEC_D8, BIT(3), BIT(3) ); // auto clear to 0 by dsp in HAL_AVD_AFEC_SetChannelChange()
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| H A D | regAVD.h | 365 #define BK_AFEC_D8 (AFEC_REG_BASE+0xD8) macro
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| /utopia/UTPA2-700.0.x/modules/vd/hal/M7621/avd/ |
| H A D | halAVD.c | 6079 _RV1(BK_AFEC_D8, 0x20),
6823 u8AfecD8=RIU_ReadByte(BK_AFEC_D8); in HAL_AVD_AFEC_McuReset()
6860 RIU_WriteByteMask (BK_AFEC_D8, u8AfecD8 & (~ BIT(3)), BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
7675 RIU_WriteByteMask (BK_AFEC_D8, u8Limit<< 4, BMASK(7:4)); in HAL_AVD_AFEC_SetSwingLimit()
7692 RIU_WriteByteMask( BK_AFEC_D8, BIT(3), BIT(3) ); // auto clear to 0 by dsp in HAL_AVD_AFEC_SetChannelChange()
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| H A D | regAVD.h | 365 #define BK_AFEC_D8 (AFEC_REG_BASE+0xD8) macro
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| /utopia/UTPA2-700.0.x/modules/vd/hal/maldives/avd/ |
| H A D | halAVD.c | 6071 _RV1(BK_AFEC_D8, 0x20),
6784 u8AfecD8=RIU_ReadByte(BK_AFEC_D8); in HAL_AVD_AFEC_McuReset()
6801 RIU_WriteByteMask (BK_AFEC_D8, u8AfecD8 & (~ BIT(3)), BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
7549 RIU_WriteByteMask (BK_AFEC_D8, u8Limit<< 4, BMASK(7:4)); in HAL_AVD_AFEC_SetSwingLimit()
7566 RIU_WriteByteMask( BK_AFEC_D8, BIT(3), BIT(3) ); // auto clear to 0 by dsp in HAL_AVD_AFEC_SetChannelChange()
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| H A D | regAVD.h | 365 #define BK_AFEC_D8 (AFEC_REG_BASE+0xD8) macro
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| /utopia/UTPA2-700.0.x/modules/vd/hal/messi/avd/ |
| H A D | halAVD.c | 2727 _RV1(BK_AFEC_D8, 0x20),
3428 u8AfecD8=RIU_ReadByte(BK_AFEC_D8); in HAL_AVD_AFEC_McuReset()
3445 RIU_WriteByteMask (BK_AFEC_D8, u8AfecD8 & (~ BIT(3)), BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
4187 RIU_WriteByteMask (BK_AFEC_D8, u8Limit<< 4, BMASK(7:4)); in HAL_AVD_AFEC_SetSwingLimit()
4204 RIU_WriteByteMask( BK_AFEC_D8, BIT(3), BIT(3) ); // auto clear to 0 by dsp in HAL_AVD_AFEC_SetChannelChange()
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| H A D | regAVD.h | 365 #define BK_AFEC_D8 (AFEC_REG_BASE+0xD8) macro
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| /utopia/UTPA2-700.0.x/modules/vd/hal/maserati/avd/ |
| H A D | halAVD.c | 6079 _RV1(BK_AFEC_D8, 0x20),
6823 u8AfecD8=RIU_ReadByte(BK_AFEC_D8); in HAL_AVD_AFEC_McuReset()
6860 RIU_WriteByteMask (BK_AFEC_D8, u8AfecD8 & (~ BIT(3)), BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
7675 RIU_WriteByteMask (BK_AFEC_D8, u8Limit<< 4, BMASK(7:4)); in HAL_AVD_AFEC_SetSwingLimit()
7692 RIU_WriteByteMask( BK_AFEC_D8, BIT(3), BIT(3) ); // auto clear to 0 by dsp in HAL_AVD_AFEC_SetChannelChange()
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| H A D | regAVD.h | 365 #define BK_AFEC_D8 (AFEC_REG_BASE+0xD8) macro
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| /utopia/UTPA2-700.0.x/modules/vd/hal/maxim/avd/ |
| H A D | halAVD.c | 6079 _RV1(BK_AFEC_D8, 0x20),
6823 u8AfecD8=RIU_ReadByte(BK_AFEC_D8); in HAL_AVD_AFEC_McuReset()
6860 RIU_WriteByteMask (BK_AFEC_D8, u8AfecD8 & (~ BIT(3)), BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
7675 RIU_WriteByteMask (BK_AFEC_D8, u8Limit<< 4, BMASK(7:4)); in HAL_AVD_AFEC_SetSwingLimit()
7692 RIU_WriteByteMask( BK_AFEC_D8, BIT(3), BIT(3) ); // auto clear to 0 by dsp in HAL_AVD_AFEC_SetChannelChange()
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| H A D | regAVD.h | 365 #define BK_AFEC_D8 (AFEC_REG_BASE+0xD8) macro
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| /utopia/UTPA2-700.0.x/modules/vd/hal/mooney/avd/ |
| H A D | halAVD.c | 2726 _RV1(BK_AFEC_D8, 0x20),
3427 u8AfecD8=RIU_ReadByte(BK_AFEC_D8); in HAL_AVD_AFEC_McuReset()
3444 RIU_WriteByteMask (BK_AFEC_D8, u8AfecD8 & (~ BIT(3)), BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
4186 RIU_WriteByteMask (BK_AFEC_D8, u8Limit<< 4, BMASK(7:4)); in HAL_AVD_AFEC_SetSwingLimit()
4203 RIU_WriteByteMask( BK_AFEC_D8, BIT(3), BIT(3) ); // auto clear to 0 by dsp in HAL_AVD_AFEC_SetChannelChange()
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| H A D | regAVD.h | 365 #define BK_AFEC_D8 (AFEC_REG_BASE+0xD8) macro
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| /utopia/UTPA2-700.0.x/modules/vd/hal/macan/avd/ |
| H A D | halAVD.c | 6073 _RV1(BK_AFEC_D8, 0x20),
6800 u8AfecD8=RIU_ReadByte(BK_AFEC_D8); in HAL_AVD_AFEC_McuReset()
6817 RIU_WriteByteMask (BK_AFEC_D8, u8AfecD8 & (~ BIT(3)), BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
7565 RIU_WriteByteMask (BK_AFEC_D8, u8Limit<< 4, BMASK(7:4)); in HAL_AVD_AFEC_SetSwingLimit()
7582 RIU_WriteByteMask( BK_AFEC_D8, BIT(3), BIT(3) ); // auto clear to 0 by dsp in HAL_AVD_AFEC_SetChannelChange()
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| H A D | regAVD.h | 365 #define BK_AFEC_D8 (AFEC_REG_BASE+0xD8) macro
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| /utopia/UTPA2-700.0.x/modules/ve/drv/ve/include/ |
| H A D | ve_Analog_Reg.h | 701 #define BK_AFEC_D8 (AFEC_REG_BASE+0xD8) macro
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