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Searched refs:BK_AFEC_D5 (Results 1 – 25 of 27) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vd/drv/avd/
H A DAVD.c2909 u8tmp = HAL_AVD_GetReg(BK_AFEC_D5); in Drv_AVD_SetFactoryPara()
2911 HAL_AVD_SetReg(BK_AFEC_D5,u8tmp |(u8Value & BIT(2))); in Drv_AVD_SetFactoryPara()
2963 u8tmp = HAL_AVD_GetReg(BK_AFEC_D5); in Drv_AVD_SetFactoryPara()
2965 HAL_AVD_SetReg(BK_AFEC_D5,u8tmp |(u8Value & BIT(3))); in Drv_AVD_SetFactoryPara()
/utopia/UTPA2-700.0.x/modules/vd/hal/mainz/avd/
H A DhalAVD.c3427 u8AfecD5=RIU_ReadByte(BK_AFEC_D5); in HAL_AVD_AFEC_McuReset()
3444 RIU_WriteByteMask (BK_AFEC_D5, u8AfecD5, BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h362 #define BK_AFEC_D5 (AFEC_REG_BASE+0xD5) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/mustang/avd/
H A DhalAVD.c6783 u8AfecD5=RIU_ReadByte(BK_AFEC_D5); in HAL_AVD_AFEC_McuReset()
6800 RIU_WriteByteMask (BK_AFEC_D5, u8AfecD5, BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h362 #define BK_AFEC_D5 (AFEC_REG_BASE+0xD5) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/M7821/avd/
H A DhalAVD.c6822 u8AfecD5=RIU_ReadByte(BK_AFEC_D5); in HAL_AVD_AFEC_McuReset()
6859 RIU_WriteByteMask (BK_AFEC_D5, u8AfecD5, BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h362 #define BK_AFEC_D5 (AFEC_REG_BASE+0xD5) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/kano/avd/
H A DhalAVD.c6822 u8AfecD5=RIU_ReadByte(BK_AFEC_D5); in HAL_AVD_AFEC_McuReset()
6859 RIU_WriteByteMask (BK_AFEC_D5, u8AfecD5, BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h362 #define BK_AFEC_D5 (AFEC_REG_BASE+0xD5) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/manhattan/avd/
H A DhalAVD.c6821 u8AfecD5=RIU_ReadByte(BK_AFEC_D5); in HAL_AVD_AFEC_McuReset()
6858 RIU_WriteByteMask (BK_AFEC_D5, u8AfecD5, BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h362 #define BK_AFEC_D5 (AFEC_REG_BASE+0xD5) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/M7621/avd/
H A DhalAVD.c6822 u8AfecD5=RIU_ReadByte(BK_AFEC_D5); in HAL_AVD_AFEC_McuReset()
6859 RIU_WriteByteMask (BK_AFEC_D5, u8AfecD5, BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h362 #define BK_AFEC_D5 (AFEC_REG_BASE+0xD5) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/maldives/avd/
H A DhalAVD.c6783 u8AfecD5=RIU_ReadByte(BK_AFEC_D5); in HAL_AVD_AFEC_McuReset()
6800 RIU_WriteByteMask (BK_AFEC_D5, u8AfecD5, BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h362 #define BK_AFEC_D5 (AFEC_REG_BASE+0xD5) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/messi/avd/
H A DhalAVD.c3427 u8AfecD5=RIU_ReadByte(BK_AFEC_D5); in HAL_AVD_AFEC_McuReset()
3444 RIU_WriteByteMask (BK_AFEC_D5, u8AfecD5, BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h362 #define BK_AFEC_D5 (AFEC_REG_BASE+0xD5) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/maserati/avd/
H A DhalAVD.c6822 u8AfecD5=RIU_ReadByte(BK_AFEC_D5); in HAL_AVD_AFEC_McuReset()
6859 RIU_WriteByteMask (BK_AFEC_D5, u8AfecD5, BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h362 #define BK_AFEC_D5 (AFEC_REG_BASE+0xD5) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/maxim/avd/
H A DhalAVD.c6822 u8AfecD5=RIU_ReadByte(BK_AFEC_D5); in HAL_AVD_AFEC_McuReset()
6859 RIU_WriteByteMask (BK_AFEC_D5, u8AfecD5, BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h362 #define BK_AFEC_D5 (AFEC_REG_BASE+0xD5) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/mooney/avd/
H A DhalAVD.c3426 u8AfecD5=RIU_ReadByte(BK_AFEC_D5); in HAL_AVD_AFEC_McuReset()
3443 RIU_WriteByteMask (BK_AFEC_D5, u8AfecD5, BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h362 #define BK_AFEC_D5 (AFEC_REG_BASE+0xD5) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/macan/avd/
H A DhalAVD.c6799 u8AfecD5=RIU_ReadByte(BK_AFEC_D5); in HAL_AVD_AFEC_McuReset()
6816 RIU_WriteByteMask (BK_AFEC_D5, u8AfecD5, BMASK(7:0)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h362 #define BK_AFEC_D5 (AFEC_REG_BASE+0xD5) macro

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