Home
last modified time | relevance | path

Searched refs:BK_AFEC_A2 (Results 1 – 25 of 27) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/vd/hal/mainz/avd/
H A DhalAVD.c2733 _RV1( BK_AFEC_A2, 0x40 ),
3665 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
3685 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
3707 RIU_WriteByteMask(BK_AFEC_A2, 0x20,(BIT(4)|BIT(5))); // Disable 2-line-delay in HAL_AVD_AFEC_SetInput()
3745 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
H A DregAVD.h311 #define BK_AFEC_A2 (AFEC_REG_BASE+0xA2) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/mustang/avd/
H A DhalAVD.c6077 _RV1( BK_AFEC_A2, 0x40 ),
7027 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
7047 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
7069 RIU_WriteByteMask(BK_AFEC_A2, 0x20,(BIT(4)|BIT(5))); // Disable 2-line-delay in HAL_AVD_AFEC_SetInput()
7107 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
H A DregAVD.h311 #define BK_AFEC_A2 (AFEC_REG_BASE+0xA2) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/M7821/avd/
H A DhalAVD.c6085 _RV1( BK_AFEC_A2, 0x40 ),
7153 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
7173 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
7195 RIU_WriteByteMask(BK_AFEC_A2, 0x20,(BIT(4)|BIT(5))); // Disable 2-line-delay in HAL_AVD_AFEC_SetInput()
7233 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
H A DregAVD.h311 #define BK_AFEC_A2 (AFEC_REG_BASE+0xA2) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/kano/avd/
H A DhalAVD.c6085 _RV1( BK_AFEC_A2, 0x40 ),
7153 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
7173 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
7195 RIU_WriteByteMask(BK_AFEC_A2, 0x20,(BIT(4)|BIT(5))); // Disable 2-line-delay in HAL_AVD_AFEC_SetInput()
7233 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
H A DregAVD.h311 #define BK_AFEC_A2 (AFEC_REG_BASE+0xA2) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/manhattan/avd/
H A DhalAVD.c6084 _RV1( BK_AFEC_A2, 0x40 ),
7100 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
7120 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
7142 RIU_WriteByteMask(BK_AFEC_A2, 0x20,(BIT(4)|BIT(5))); // Disable 2-line-delay in HAL_AVD_AFEC_SetInput()
7180 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
H A DregAVD.h311 #define BK_AFEC_A2 (AFEC_REG_BASE+0xA2) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/M7621/avd/
H A DhalAVD.c6085 _RV1( BK_AFEC_A2, 0x40 ),
7153 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
7173 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
7195 RIU_WriteByteMask(BK_AFEC_A2, 0x20,(BIT(4)|BIT(5))); // Disable 2-line-delay in HAL_AVD_AFEC_SetInput()
7233 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
H A DregAVD.h311 #define BK_AFEC_A2 (AFEC_REG_BASE+0xA2) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/maldives/avd/
H A DhalAVD.c6077 _RV1( BK_AFEC_A2, 0x40 ),
7027 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
7047 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
7069 RIU_WriteByteMask(BK_AFEC_A2, 0x20,(BIT(4)|BIT(5))); // Disable 2-line-delay in HAL_AVD_AFEC_SetInput()
7107 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
H A DregAVD.h311 #define BK_AFEC_A2 (AFEC_REG_BASE+0xA2) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/messi/avd/
H A DhalAVD.c2733 _RV1( BK_AFEC_A2, 0x40 ),
3665 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
3685 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
3707 RIU_WriteByteMask(BK_AFEC_A2, 0x20,(BIT(4)|BIT(5))); // Disable 2-line-delay in HAL_AVD_AFEC_SetInput()
3745 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
H A DregAVD.h311 #define BK_AFEC_A2 (AFEC_REG_BASE+0xA2) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/maserati/avd/
H A DhalAVD.c6085 _RV1( BK_AFEC_A2, 0x40 ),
7153 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
7173 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
7195 RIU_WriteByteMask(BK_AFEC_A2, 0x20,(BIT(4)|BIT(5))); // Disable 2-line-delay in HAL_AVD_AFEC_SetInput()
7233 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
H A DregAVD.h311 #define BK_AFEC_A2 (AFEC_REG_BASE+0xA2) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/maxim/avd/
H A DhalAVD.c6085 _RV1( BK_AFEC_A2, 0x40 ),
7153 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
7173 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
7195 RIU_WriteByteMask(BK_AFEC_A2, 0x20,(BIT(4)|BIT(5))); // Disable 2-line-delay in HAL_AVD_AFEC_SetInput()
7233 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
H A DregAVD.h311 #define BK_AFEC_A2 (AFEC_REG_BASE+0xA2) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/mooney/avd/
H A DhalAVD.c2732 _RV1( BK_AFEC_A2, 0x40 ),
3664 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
3684 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
3706 RIU_WriteByteMask(BK_AFEC_A2, 0x20,(BIT(4)|BIT(5))); // Disable 2-line-delay in HAL_AVD_AFEC_SetInput()
3744 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
H A DregAVD.h311 #define BK_AFEC_A2 (AFEC_REG_BASE+0xA2) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/macan/avd/
H A DhalAVD.c6079 _RV1( BK_AFEC_A2, 0x40 ),
7043 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
7063 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
7085 RIU_WriteByteMask(BK_AFEC_A2, 0x20,(BIT(4)|BIT(5))); // Disable 2-line-delay in HAL_AVD_AFEC_SetInput()
7123 RIU_WriteByteMask(BK_AFEC_A2, 0x00,(BIT(4)|BIT(5))); // 2-line-delay ctrl by VD-DSP in HAL_AVD_AFEC_SetInput()
H A DregAVD.h311 #define BK_AFEC_A2 (AFEC_REG_BASE+0xA2) macro
/utopia/UTPA2-700.0.x/modules/vd/drv/avd/
H A DAVD.c1155 HAL_AVD_SetReg(BK_AFEC_A2,(HAL_AVD_GetReg(BK_AFEC_A2)&0xCF)|0x20); in _Drv_AVD_SCART_Monitor()
1198 HAL_AVD_SetReg(BK_AFEC_A2,(HAL_AVD_GetReg(BK_AFEC_A2)&0xCF)); in _Drv_AVD_SCART_Monitor()

12