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Searched refs:BK_AFEC_44 (Results 1 – 25 of 27) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vd/drv/avd/
H A DAVD.c2949 HAL_AVD_SetReg(BK_AFEC_44,u8Value); in Drv_AVD_SetFactoryPara()
3066 HAL_AVD_SetReg(BK_AFEC_44, (u16FineGain)& 0xFF);//AFEC_44[7:0], fine gain in Drv_AVD_SetAutoFineGainToFixed()
3315 HAL_AVD_SetReg(BK_AFEC_44, (u16FineGain)& 0xFF);//AFEC_44[7:0], fine gain in Drv_AVD_GetDSPFineGain()
/utopia/UTPA2-700.0.x/modules/vd/hal/mustang/avd/
H A DregAVD.h217 #define BK_AFEC_44 (AFEC_REG_BASE+0x44) macro
H A DhalAVD.c7487 RIU_WriteByte (BK_AFEC_44, u8AgcFineGain); in HAL_AVD_AFEC_AGCSetFineGain()
/utopia/UTPA2-700.0.x/modules/vd/hal/kano/avd/
H A DregAVD.h217 #define BK_AFEC_44 (AFEC_REG_BASE+0x44) macro
H A DhalAVD.c7613 RIU_WriteByte (BK_AFEC_44, u8AgcFineGain); in HAL_AVD_AFEC_AGCSetFineGain()
/utopia/UTPA2-700.0.x/modules/vd/hal/maxim/avd/
H A DregAVD.h217 #define BK_AFEC_44 (AFEC_REG_BASE+0x44) macro
H A DhalAVD.c7613 RIU_WriteByte (BK_AFEC_44, u8AgcFineGain); in HAL_AVD_AFEC_AGCSetFineGain()
/utopia/UTPA2-700.0.x/modules/vd/hal/macan/avd/
H A DregAVD.h217 #define BK_AFEC_44 (AFEC_REG_BASE+0x44) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/messi/avd/
H A DregAVD.h217 #define BK_AFEC_44 (AFEC_REG_BASE+0x44) macro
H A DhalAVD.c4125 RIU_WriteByte (BK_AFEC_44, u8AgcFineGain); in HAL_AVD_AFEC_AGCSetFineGain()
/utopia/UTPA2-700.0.x/modules/vd/hal/manhattan/avd/
H A DregAVD.h217 #define BK_AFEC_44 (AFEC_REG_BASE+0x44) macro
H A DhalAVD.c7560 RIU_WriteByte (BK_AFEC_44, u8AgcFineGain); in HAL_AVD_AFEC_AGCSetFineGain()
/utopia/UTPA2-700.0.x/modules/vd/hal/maserati/avd/
H A DregAVD.h217 #define BK_AFEC_44 (AFEC_REG_BASE+0x44) macro
H A DhalAVD.c7613 RIU_WriteByte (BK_AFEC_44, u8AgcFineGain); in HAL_AVD_AFEC_AGCSetFineGain()
/utopia/UTPA2-700.0.x/modules/vd/hal/M7621/avd/
H A DregAVD.h217 #define BK_AFEC_44 (AFEC_REG_BASE+0x44) macro
H A DhalAVD.c7613 RIU_WriteByte (BK_AFEC_44, u8AgcFineGain); in HAL_AVD_AFEC_AGCSetFineGain()
/utopia/UTPA2-700.0.x/modules/vd/hal/mainz/avd/
H A DregAVD.h217 #define BK_AFEC_44 (AFEC_REG_BASE+0x44) macro
H A DhalAVD.c4125 RIU_WriteByte (BK_AFEC_44, u8AgcFineGain); in HAL_AVD_AFEC_AGCSetFineGain()
/utopia/UTPA2-700.0.x/modules/vd/hal/maldives/avd/
H A DregAVD.h217 #define BK_AFEC_44 (AFEC_REG_BASE+0x44) macro
H A DhalAVD.c7487 RIU_WriteByte (BK_AFEC_44, u8AgcFineGain); in HAL_AVD_AFEC_AGCSetFineGain()
/utopia/UTPA2-700.0.x/modules/vd/hal/M7821/avd/
H A DregAVD.h217 #define BK_AFEC_44 (AFEC_REG_BASE+0x44) macro
H A DhalAVD.c7613 RIU_WriteByte (BK_AFEC_44, u8AgcFineGain); in HAL_AVD_AFEC_AGCSetFineGain()
/utopia/UTPA2-700.0.x/modules/vd/hal/mooney/avd/
H A DregAVD.h217 #define BK_AFEC_44 (AFEC_REG_BASE+0x44) macro
H A DhalAVD.c4124 RIU_WriteByte (BK_AFEC_44, u8AgcFineGain); in HAL_AVD_AFEC_AGCSetFineGain()
/utopia/UTPA2-700.0.x/modules/ve/drv/ve/include/
H A Dve_Analog_Reg.h553 #define BK_AFEC_44 (AFEC_REG_BASE+0x44) macro

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