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Searched refs:BK_AFEC_16 (Results 1 – 25 of 26) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vd/hal/mainz/avd/
H A DhalAVD.c2715 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
3432 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
3434 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h171 #define BK_AFEC_16 (AFEC_REG_BASE+0x16) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/mustang/avd/
H A DhalAVD.c6059 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
6788 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6790 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h171 #define BK_AFEC_16 (AFEC_REG_BASE+0x16) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/M7821/avd/
H A DhalAVD.c6067 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
6827 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6836 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h171 #define BK_AFEC_16 (AFEC_REG_BASE+0x16) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/kano/avd/
H A DhalAVD.c6067 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
6827 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6836 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h171 #define BK_AFEC_16 (AFEC_REG_BASE+0x16) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/manhattan/avd/
H A DhalAVD.c6066 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
6826 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6835 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h171 #define BK_AFEC_16 (AFEC_REG_BASE+0x16) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/M7621/avd/
H A DhalAVD.c6067 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
6827 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6836 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h171 #define BK_AFEC_16 (AFEC_REG_BASE+0x16) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/maldives/avd/
H A DhalAVD.c6059 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
6788 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6790 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h171 #define BK_AFEC_16 (AFEC_REG_BASE+0x16) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/messi/avd/
H A DhalAVD.c2715 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
3432 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
3434 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h171 #define BK_AFEC_16 (AFEC_REG_BASE+0x16) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/maserati/avd/
H A DhalAVD.c6067 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
6827 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6836 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h171 #define BK_AFEC_16 (AFEC_REG_BASE+0x16) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/maxim/avd/
H A DhalAVD.c6067 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
6827 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6836 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h171 #define BK_AFEC_16 (AFEC_REG_BASE+0x16) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/mooney/avd/
H A DhalAVD.c2714 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
3431 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
3433 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h171 #define BK_AFEC_16 (AFEC_REG_BASE+0x16) macro
/utopia/UTPA2-700.0.x/modules/vd/hal/macan/avd/
H A DhalAVD.c6061 … _RV1(BK_AFEC_16, 0x05), // 3516[4:2]=010--> XIU interface retry mode, 3516[0]=1 check false sync
6804 RIU_WriteRegBit(BK_AFEC_16, ENABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
6806 RIU_WriteRegBit(BK_AFEC_16, DISABLE, BIT(7)); in HAL_AVD_AFEC_McuReset()
H A DregAVD.h171 #define BK_AFEC_16 (AFEC_REG_BASE+0x16) macro
/utopia/UTPA2-700.0.x/modules/ve/drv/ve/include/
H A Dve_Analog_Reg.h507 #define BK_AFEC_16 (AFEC_REG_BASE+0x16) macro

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