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Searched refs:BDMA_SET_CH0_REG (Results 1 – 15 of 15) sorted by relevance

/utopia/UTPA2-700.0.x/modules/bdma/hal/manhattan/bdma/
H A DregBDMA.h118 #define BDMA_SET_CH0_REG(x) (BDMA_REG_CH0_BASE+(x)) macro
119 #define BDMA_SET_CH1_REG(x) (BDMA_SET_CH0_REG(x)+BDMA_CH_REG_OFFSET)
121 #define BDMA_REG_CH0_CTRL BDMA_SET_CH0_REG(0UL)
122 #define BDMA_REG_CH0_STATUS BDMA_SET_CH0_REG(0x02UL)
123 #define BDMA_REG_CH0_SRC_SEL BDMA_SET_CH0_REG(0x04UL)
124 #define BDMA_REG_CH0_DST_SEL BDMA_SET_CH0_REG(0x05UL)
125 #define BDMA_REG_CH0_MISC BDMA_SET_CH0_REG(0x06UL)
126 #define BDMA_REG_CH0_DWUM_CNT BDMA_SET_CH0_REG(0x07UL)
127 #define BDMA_REG_CH0_SRC_ADDR_L BDMA_SET_CH0_REG(0x08UL)
128 #define BDMA_REG_CH0_SRC_ADDR_H BDMA_SET_CH0_REG(0x0AUL)
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/utopia/UTPA2-700.0.x/modules/bdma/hal/macan/bdma/
H A DregBDMA.h118 #define BDMA_SET_CH0_REG(x) (BDMA_REG_CH0_BASE+(x)) macro
119 #define BDMA_SET_CH1_REG(x) (BDMA_SET_CH0_REG(x)+BDMA_CH_REG_OFFSET)
121 #define BDMA_REG_CH0_CTRL BDMA_SET_CH0_REG(0UL)
122 #define BDMA_REG_CH0_STATUS BDMA_SET_CH0_REG(0x02UL)
123 #define BDMA_REG_CH0_SRC_SEL BDMA_SET_CH0_REG(0x04UL)
124 #define BDMA_REG_CH0_DST_SEL BDMA_SET_CH0_REG(0x05UL)
125 #define BDMA_REG_CH0_MISC BDMA_SET_CH0_REG(0x06UL)
126 #define BDMA_REG_CH0_DWUM_CNT BDMA_SET_CH0_REG(0x07UL)
127 #define BDMA_REG_CH0_SRC_ADDR_L BDMA_SET_CH0_REG(0x08UL)
128 #define BDMA_REG_CH0_SRC_ADDR_H BDMA_SET_CH0_REG(0x0AUL)
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/utopia/UTPA2-700.0.x/modules/bdma/hal/mustang/bdma/
H A DregBDMA.h118 #define BDMA_SET_CH0_REG(x) (BDMA_REG_CH0_BASE+(x)) macro
119 #define BDMA_SET_CH1_REG(x) (BDMA_SET_CH0_REG(x)+BDMA_CH_REG_OFFSET)
121 #define BDMA_REG_CH0_CTRL BDMA_SET_CH0_REG(0)
122 #define BDMA_REG_CH0_STATUS BDMA_SET_CH0_REG(0x02)
123 #define BDMA_REG_CH0_SRC_SEL BDMA_SET_CH0_REG(0x04)
124 #define BDMA_REG_CH0_DST_SEL BDMA_SET_CH0_REG(0x05)
125 #define BDMA_REG_CH0_MISC BDMA_SET_CH0_REG(0x06)
126 #define BDMA_REG_CH0_DWUM_CNT BDMA_SET_CH0_REG(0x07)
127 #define BDMA_REG_CH0_SRC_ADDR_L BDMA_SET_CH0_REG(0x08)
128 #define BDMA_REG_CH0_SRC_ADDR_H BDMA_SET_CH0_REG(0x0A)
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/utopia/UTPA2-700.0.x/modules/bdma/hal/messi/bdma/
H A DregBDMA.h118 #define BDMA_SET_CH0_REG(x) (BDMA_REG_CH0_BASE+(x)) macro
119 #define BDMA_SET_CH1_REG(x) (BDMA_SET_CH0_REG(x)+BDMA_CH_REG_OFFSET)
121 #define BDMA_REG_CH0_CTRL BDMA_SET_CH0_REG(0UL)
122 #define BDMA_REG_CH0_STATUS BDMA_SET_CH0_REG(0x02UL)
123 #define BDMA_REG_CH0_SRC_SEL BDMA_SET_CH0_REG(0x04UL)
124 #define BDMA_REG_CH0_DST_SEL BDMA_SET_CH0_REG(0x05UL)
125 #define BDMA_REG_CH0_MISC BDMA_SET_CH0_REG(0x06UL)
126 #define BDMA_REG_CH0_DWUM_CNT BDMA_SET_CH0_REG(0x07UL)
127 #define BDMA_REG_CH0_SRC_ADDR_L BDMA_SET_CH0_REG(0x08UL)
128 #define BDMA_REG_CH0_SRC_ADDR_H BDMA_SET_CH0_REG(0x0AUL)
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/utopia/UTPA2-700.0.x/modules/bdma/hal/mooney/bdma/
H A DregBDMA.h118 #define BDMA_SET_CH0_REG(x) (BDMA_REG_CH0_BASE+(x)) macro
119 #define BDMA_SET_CH1_REG(x) (BDMA_SET_CH0_REG(x)+BDMA_CH_REG_OFFSET)
121 #define BDMA_REG_CH0_CTRL BDMA_SET_CH0_REG(0UL)
122 #define BDMA_REG_CH0_STATUS BDMA_SET_CH0_REG(0x02UL)
123 #define BDMA_REG_CH0_SRC_SEL BDMA_SET_CH0_REG(0x04UL)
124 #define BDMA_REG_CH0_DST_SEL BDMA_SET_CH0_REG(0x05UL)
125 #define BDMA_REG_CH0_MISC BDMA_SET_CH0_REG(0x06UL)
126 #define BDMA_REG_CH0_DWUM_CNT BDMA_SET_CH0_REG(0x07UL)
127 #define BDMA_REG_CH0_SRC_ADDR_L BDMA_SET_CH0_REG(0x08UL)
128 #define BDMA_REG_CH0_SRC_ADDR_H BDMA_SET_CH0_REG(0x0AUL)
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/utopia/UTPA2-700.0.x/modules/bdma/hal/maldives/bdma/
H A DregBDMA.h118 #define BDMA_SET_CH0_REG(x) (BDMA_REG_CH0_BASE+(x)) macro
119 #define BDMA_SET_CH1_REG(x) (BDMA_SET_CH0_REG(x)+BDMA_CH_REG_OFFSET)
121 #define BDMA_REG_CH0_CTRL BDMA_SET_CH0_REG(0)
122 #define BDMA_REG_CH0_STATUS BDMA_SET_CH0_REG(0x02)
123 #define BDMA_REG_CH0_SRC_SEL BDMA_SET_CH0_REG(0x04)
124 #define BDMA_REG_CH0_DST_SEL BDMA_SET_CH0_REG(0x05)
125 #define BDMA_REG_CH0_MISC BDMA_SET_CH0_REG(0x06)
126 #define BDMA_REG_CH0_DWUM_CNT BDMA_SET_CH0_REG(0x07)
127 #define BDMA_REG_CH0_SRC_ADDR_L BDMA_SET_CH0_REG(0x08)
128 #define BDMA_REG_CH0_SRC_ADDR_H BDMA_SET_CH0_REG(0x0A)
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/utopia/UTPA2-700.0.x/modules/bdma/hal/mainz/bdma/
H A DregBDMA.h118 #define BDMA_SET_CH0_REG(x) (BDMA_REG_CH0_BASE+(x)) macro
119 #define BDMA_SET_CH1_REG(x) (BDMA_SET_CH0_REG(x)+BDMA_CH_REG_OFFSET)
121 #define BDMA_REG_CH0_CTRL BDMA_SET_CH0_REG(0UL)
122 #define BDMA_REG_CH0_STATUS BDMA_SET_CH0_REG(0x02UL)
123 #define BDMA_REG_CH0_SRC_SEL BDMA_SET_CH0_REG(0x04UL)
124 #define BDMA_REG_CH0_DST_SEL BDMA_SET_CH0_REG(0x05UL)
125 #define BDMA_REG_CH0_MISC BDMA_SET_CH0_REG(0x06UL)
126 #define BDMA_REG_CH0_DWUM_CNT BDMA_SET_CH0_REG(0x07UL)
127 #define BDMA_REG_CH0_SRC_ADDR_L BDMA_SET_CH0_REG(0x08UL)
128 #define BDMA_REG_CH0_SRC_ADDR_H BDMA_SET_CH0_REG(0x0AUL)
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/utopia/UTPA2-700.0.x/modules/bdma/hal/M7821/bdma/
H A DregBDMA.h118 #define BDMA_SET_CH0_REG(x) (BDMA_REG_CH0_BASE+(x)) macro
119 #define BDMA_SET_CH1_REG(x) (BDMA_SET_CH0_REG(x)+BDMA_CH_REG_OFFSET)
121 #define BDMA_REG_CH0_CTRL BDMA_SET_CH0_REG(0UL)
122 #define BDMA_REG_CH0_STATUS BDMA_SET_CH0_REG(0x02UL)
123 #define BDMA_REG_CH0_SRC_SEL BDMA_SET_CH0_REG(0x04UL)
124 #define BDMA_REG_CH0_DST_SEL BDMA_SET_CH0_REG(0x05UL)
125 #define BDMA_REG_CH0_MISC BDMA_SET_CH0_REG(0x06UL)
126 #define BDMA_REG_CH0_DWUM_CNT BDMA_SET_CH0_REG(0x07UL)
127 #define BDMA_REG_CH0_SRC_ADDR_L BDMA_SET_CH0_REG(0x08UL)
128 #define BDMA_REG_CH0_SRC_ADDR_H BDMA_SET_CH0_REG(0x0AUL)
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/utopia/UTPA2-700.0.x/modules/bdma/hal/maserati/bdma/
H A DregBDMA.h118 #define BDMA_SET_CH0_REG(x) (BDMA_REG_CH0_BASE+(x)) macro
119 #define BDMA_SET_CH1_REG(x) (BDMA_SET_CH0_REG(x)+BDMA_CH_REG_OFFSET)
121 #define BDMA_REG_CH0_CTRL BDMA_SET_CH0_REG(0UL)
122 #define BDMA_REG_CH0_STATUS BDMA_SET_CH0_REG(0x02UL)
123 #define BDMA_REG_CH0_SRC_SEL BDMA_SET_CH0_REG(0x04UL)
124 #define BDMA_REG_CH0_DST_SEL BDMA_SET_CH0_REG(0x05UL)
125 #define BDMA_REG_CH0_MISC BDMA_SET_CH0_REG(0x06UL)
126 #define BDMA_REG_CH0_DWUM_CNT BDMA_SET_CH0_REG(0x07UL)
127 #define BDMA_REG_CH0_SRC_ADDR_L BDMA_SET_CH0_REG(0x08UL)
128 #define BDMA_REG_CH0_SRC_ADDR_H BDMA_SET_CH0_REG(0x0AUL)
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/utopia/UTPA2-700.0.x/modules/bdma/hal/maxim/bdma/
H A DregBDMA.h118 #define BDMA_SET_CH0_REG(x) (BDMA_REG_CH0_BASE+(x)) macro
119 #define BDMA_SET_CH1_REG(x) (BDMA_SET_CH0_REG(x)+BDMA_CH_REG_OFFSET)
121 #define BDMA_REG_CH0_CTRL BDMA_SET_CH0_REG(0UL)
122 #define BDMA_REG_CH0_STATUS BDMA_SET_CH0_REG(0x02UL)
123 #define BDMA_REG_CH0_SRC_SEL BDMA_SET_CH0_REG(0x04UL)
124 #define BDMA_REG_CH0_DST_SEL BDMA_SET_CH0_REG(0x05UL)
125 #define BDMA_REG_CH0_MISC BDMA_SET_CH0_REG(0x06UL)
126 #define BDMA_REG_CH0_DWUM_CNT BDMA_SET_CH0_REG(0x07UL)
127 #define BDMA_REG_CH0_SRC_ADDR_L BDMA_SET_CH0_REG(0x08UL)
128 #define BDMA_REG_CH0_SRC_ADDR_H BDMA_SET_CH0_REG(0x0AUL)
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/utopia/UTPA2-700.0.x/modules/bdma/hal/M7621/bdma/
H A DregBDMA.h118 #define BDMA_SET_CH0_REG(x) (BDMA_REG_CH0_BASE+(x)) macro
119 #define BDMA_SET_CH1_REG(x) (BDMA_SET_CH0_REG(x)+BDMA_CH_REG_OFFSET)
121 #define BDMA_REG_CH0_CTRL BDMA_SET_CH0_REG(0UL)
122 #define BDMA_REG_CH0_STATUS BDMA_SET_CH0_REG(0x02UL)
123 #define BDMA_REG_CH0_SRC_SEL BDMA_SET_CH0_REG(0x04UL)
124 #define BDMA_REG_CH0_DST_SEL BDMA_SET_CH0_REG(0x05UL)
125 #define BDMA_REG_CH0_MISC BDMA_SET_CH0_REG(0x06UL)
126 #define BDMA_REG_CH0_DWUM_CNT BDMA_SET_CH0_REG(0x07UL)
127 #define BDMA_REG_CH0_SRC_ADDR_L BDMA_SET_CH0_REG(0x08UL)
128 #define BDMA_REG_CH0_SRC_ADDR_H BDMA_SET_CH0_REG(0x0AUL)
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/utopia/UTPA2-700.0.x/modules/bdma/hal/kano/bdma/
H A DregBDMA.h118 #define BDMA_SET_CH0_REG(x) (BDMA_REG_CH0_BASE+(x)) macro
119 #define BDMA_SET_CH1_REG(x) (BDMA_SET_CH0_REG(x)+BDMA_CH_REG_OFFSET)
121 #define BDMA_REG_CH0_CTRL BDMA_SET_CH0_REG(0UL)
122 #define BDMA_REG_CH0_STATUS BDMA_SET_CH0_REG(0x02UL)
123 #define BDMA_REG_CH0_SRC_SEL BDMA_SET_CH0_REG(0x04UL)
124 #define BDMA_REG_CH0_DST_SEL BDMA_SET_CH0_REG(0x05UL)
125 #define BDMA_REG_CH0_MISC BDMA_SET_CH0_REG(0x06UL)
126 #define BDMA_REG_CH0_DWUM_CNT BDMA_SET_CH0_REG(0x07UL)
127 #define BDMA_REG_CH0_SRC_ADDR_L BDMA_SET_CH0_REG(0x08UL)
128 #define BDMA_REG_CH0_SRC_ADDR_H BDMA_SET_CH0_REG(0x0AUL)
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/utopia/UTPA2-700.0.x/modules/bdma/hal/k6/bdma/
H A DregBDMA.h118 #define BDMA_SET_CH0_REG(x) (BDMA_REG_CH0_BASE+(x)) macro
119 #define BDMA_SET_CH1_REG(x) (BDMA_SET_CH0_REG(x)+BDMA_CH_REG_OFFSET)
121 #define BDMA_REG_CH0_CTRL BDMA_SET_CH0_REG(0UL)
122 #define BDMA_REG_CH0_STATUS BDMA_SET_CH0_REG(0x02UL)
123 #define BDMA_REG_CH0_SRC_SEL BDMA_SET_CH0_REG(0x04UL)
124 #define BDMA_REG_CH0_DST_SEL BDMA_SET_CH0_REG(0x05UL)
125 #define BDMA_REG_CH0_MISC BDMA_SET_CH0_REG(0x06UL)
126 #define BDMA_REG_CH0_DWUM_CNT BDMA_SET_CH0_REG(0x07UL)
127 #define BDMA_REG_CH0_SRC_ADDR_L BDMA_SET_CH0_REG(0x08UL)
128 #define BDMA_REG_CH0_SRC_ADDR_H BDMA_SET_CH0_REG(0x0AUL)
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/utopia/UTPA2-700.0.x/modules/bdma/hal/curry/bdma/
H A DregBDMA.h118 #define BDMA_SET_CH0_REG(x) (BDMA_REG_CH0_BASE+(x)) macro
119 #define BDMA_SET_CH1_REG(x) (BDMA_SET_CH0_REG(x)+BDMA_CH_REG_OFFSET)
121 #define BDMA_REG_CH0_CTRL BDMA_SET_CH0_REG(0UL)
122 #define BDMA_REG_CH0_STATUS BDMA_SET_CH0_REG(0x02UL)
123 #define BDMA_REG_CH0_SRC_SEL BDMA_SET_CH0_REG(0x04UL)
124 #define BDMA_REG_CH0_DST_SEL BDMA_SET_CH0_REG(0x05UL)
125 #define BDMA_REG_CH0_MISC BDMA_SET_CH0_REG(0x06UL)
126 #define BDMA_REG_CH0_DWUM_CNT BDMA_SET_CH0_REG(0x07UL)
127 #define BDMA_REG_CH0_SRC_ADDR_L BDMA_SET_CH0_REG(0x08UL)
128 #define BDMA_REG_CH0_SRC_ADDR_H BDMA_SET_CH0_REG(0x0AUL)
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/utopia/UTPA2-700.0.x/modules/bdma/hal/k6lite/bdma/
H A DregBDMA.h118 #define BDMA_SET_CH0_REG(x) (BDMA_REG_CH0_BASE+(x)) macro
119 #define BDMA_SET_CH1_REG(x) (BDMA_SET_CH0_REG(x)+BDMA_CH_REG_OFFSET)
121 #define BDMA_REG_CH0_CTRL BDMA_SET_CH0_REG(0UL)
122 #define BDMA_REG_CH0_STATUS BDMA_SET_CH0_REG(0x02UL)
123 #define BDMA_REG_CH0_SRC_SEL BDMA_SET_CH0_REG(0x04UL)
124 #define BDMA_REG_CH0_DST_SEL BDMA_SET_CH0_REG(0x05UL)
125 #define BDMA_REG_CH0_MISC BDMA_SET_CH0_REG(0x06UL)
126 #define BDMA_REG_CH0_DWUM_CNT BDMA_SET_CH0_REG(0x07UL)
127 #define BDMA_REG_CH0_SRC_ADDR_L BDMA_SET_CH0_REG(0x08UL)
128 #define BDMA_REG_CH0_SRC_ADDR_H BDMA_SET_CH0_REG(0x0AUL)
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