Searched refs:reg_val (Results 1 – 2 of 2) sorted by relevance
633 RK_U32 *reg_val = reg->val; in h264e_vepu1_get_mbrc() local635 mb_rc->hw_status = reg_val[VEPU_REG_INTERRUPT / 4]; in h264e_vepu1_get_mbrc()636 mb_rc->out_strm_size = reg_val[VEPU_REG_STR_BUF_LIMIT / 4] / 8 - mb_rc->hdr_free_size; in h264e_vepu1_get_mbrc()637 mb_rc->qp_sum = VEPU_REG_QP_SUM(reg_val[VEPU_REG_MAD_CTRL / 4]); in h264e_vepu1_get_mbrc()638 mb_rc->less_mad_count = VEPU_REG_MB_CNT_SET(reg_val[VEPU_REG_MB_CTRL / 4]); in h264e_vepu1_get_mbrc()639 mb_rc->rlc_count = VEPU_REG_RLC_SUM_OUT(reg_val[VEPU_REG_RLC_CTRL / 4]); in h264e_vepu1_get_mbrc()642 RK_U32 cpt = VEPU_REG_CHECKPOINT_RESULT(reg_val[cpt_idx]); in h264e_vepu1_get_mbrc()
698 RK_U32 *reg_val = reg->val; in h264e_vepu2_get_mbrc() local700 mb_rc->hw_status = reg_val[VEPU_REG_INTERRUPT / 4]; in h264e_vepu2_get_mbrc()701 mb_rc->out_strm_size = reg_val[VEPU_REG_STR_BUF_LIMIT / 4] / 8 - mb_rc->hdr_free_size; in h264e_vepu2_get_mbrc()702 mb_rc->qp_sum = ((reg_val[VEPU_REG_QP_SUM_DIV2 / 4] >> 11) & 0x001fffff) * 2; in h264e_vepu2_get_mbrc()703 mb_rc->less_mad_count = (reg_val[VEPU_REG_MB_CTRL / 4] >> 16) & 0xffff; in h264e_vepu2_get_mbrc()704 mb_rc->rlc_count = reg_val[VEPU_REG_RLC_SUM / 4] & 0x3fffff; in h264e_vepu2_get_mbrc()707 RK_U32 cpt = VEPU_REG_CHECKPOINT_RESULT(reg_val[cpt_idx]); in h264e_vepu2_get_mbrc()