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Searched refs:VEPU_REG_CHECKPOINT (Results 1 – 4 of 4) sorted by relevance

/rockchip-linux_mpp/mpp/hal/vpu/h264e/
H A Dhal_h264e_vepu1_v2.c401 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(0), val); in hal_h264e_vepu1_gen_regs_v2()
405 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(1), val); in hal_h264e_vepu1_gen_regs_v2()
409 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(2), val); in hal_h264e_vepu1_gen_regs_v2()
413 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(3), val); in hal_h264e_vepu1_gen_regs_v2()
417 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(4), val); in hal_h264e_vepu1_gen_regs_v2()
632 RK_U32 cpt_idx = VEPU_REG_CHECKPOINT(0) / 4; in h264e_vepu1_get_mbrc()
H A Dhal_h264e_vepu2_v2.c438 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(0), val); in hal_h264e_vepu2_gen_regs_v2()
442 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(1), val); in hal_h264e_vepu2_gen_regs_v2()
446 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(2), val); in hal_h264e_vepu2_gen_regs_v2()
450 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(3), val); in hal_h264e_vepu2_gen_regs_v2()
454 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(4), val); in hal_h264e_vepu2_gen_regs_v2()
697 RK_U32 cpt_idx = VEPU_REG_CHECKPOINT(0) / 4; in h264e_vepu2_get_mbrc()
H A Dhal_h264e_vepu1_reg_tbl.h136 #define VEPU_REG_CHECKPOINT(i) (0x070 + ((i) * 0x4)) macro
H A Dhal_h264e_vepu2_reg_tbl.h136 #define VEPU_REG_CHECKPOINT(i) (0x104 + ((i) * 0x4)) macro