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Searched refs:SPSPPS_ALIGNED_SIZE (Results 1 – 4 of 4) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkdec/h265d/
H A Dhal_h265d_vdpu384a.c41 #define SPSPPS_ALIGNED_SIZE (MPP_ALIGN(2181 + 64, 128) / 8) // byte, 2181 bit + Reserve… macro
43 #define INFO_BUFFER_SIZE (SPSPPS_ALIGNED_SIZE + SCALIST_ALIGNED_SIZE)
47 #define SCALIST_OFFSET(pos) (SPSPPS_OFFSET(pos) + SPSPPS_ALIGNED_SIZE)
103 reg_ctx->pps_buf = mpp_calloc(RK_U8, SPSPPS_ALIGNED_SIZE); in hal_h265d_vdpu384a_init()
373 mpp_set_bitput_ctx(&bp, pps_packet, SPSPPS_ALIGNED_SIZE / 8); in hal_h265d_v345_output_pps_packet()
605 memcpy(pps_ptr, reg_ctx->pps_buf, SPSPPS_ALIGNED_SIZE); in hal_h265d_v345_output_pps_packet()
1093 hw_regs->h265d_paras.reg67_global_len = SPSPPS_ALIGNED_SIZE / 16; in hal_h265d_vdpu384a_gen_regs()
H A Dhal_h265d_vdpu382.c86 #define SPSPPS_ALIGNED_SIZE (MPP_ALIGN(112 * 64, SZ_4K)) macro
89 #define INFO_BUFFER_SIZE (SPSPPS_ALIGNED_SIZE + RPS_ALIGEND_SIZE + SCALIST_ALIGNED_S…
94 #define RPS_OFFSET(pos) (SPSPPS_OFFSET(pos) + SPSPPS_ALIGNED_SIZE)
H A Dhal_h265d_vdpu34x.c88 #define SPSPPS_ALIGNED_SIZE (MPP_ALIGN(112 * 64, SZ_4K)) macro
91 #define INFO_BUFFER_SIZE (SPSPPS_ALIGNED_SIZE + RPS_ALIGEND_SIZE + SCALIST_ALIGNED_S…
96 #define RPS_OFFSET(pos) (SPSPPS_OFFSET(pos) + SPSPPS_ALIGNED_SIZE)
H A Dhal_h265d_vdpu383.c59 #define SPSPPS_ALIGNED_SIZE (MPP_ALIGN(176, SZ_4K)) macro
62 #define INFO_BUFFER_SIZE (SPSPPS_ALIGNED_SIZE + RPS_ALIGEND_SIZE + SCALIST_ALIGNED_S…
67 #define RPS_OFFSET(pos) (SPSPPS_OFFSET(pos) + SPSPPS_ALIGNED_SIZE)