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Searched refs:pll_regs (Results 1 – 6 of 6) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/mx27/
H A Dgeneric.c47 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in clk_in_26m()
59 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_mpllclk()
73 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_armclk()
88 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_ahbclk()
100 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_spllclk()
119 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk1()
126 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk2()
133 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk3()
140 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk4()
182 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in cpu_eth_init()
H A Dtimer.c92 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in timer_init()
/rk3399_rockchip-uboot/arch/mips/mach-ath79/ar934x/
H A Dclk.c108 void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE, in ar934x_pll_init() local
168 setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
170 setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
172 setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
177 pll_regs + AR934X_PLL_CPU_CONFIG_REG); in ar934x_pll_init()
180 pll_regs + AR934X_PLL_DDR_CONFIG_REG); in ar934x_pll_init()
191 pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG); in ar934x_pll_init()
198 clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
200 clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
202 clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
[all …]
/rk3399_rockchip-uboot/arch/arm/lib/
H A Dasm-offsets.c81 DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); in main()
82 DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0)); in main()
83 DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0)); in main()
84 DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0)); in main()
85 DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1)); in main()
86 DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0)); in main()
87 DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1)); in main()
/rk3399_rockchip-uboot/board/armadeus/apf27/
H A Dfpga.c194 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in apf27_fpga_setup()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx27/
H A Dimx-regs.h115 struct pll_regs { struct