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Searched refs:pll_m (Results 1 – 8 of 8) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-keystone/
H A Dcmd_clock.c18 .pll_m = 16,
46 cmd_pll_data.pll_m = simple_strtoul(argv[2], NULL, 10); in do_pll_cmd()
51 cmd_pll_data.pll, cmd_pll_data.pll_m, in do_pll_cmd()
H A Dclock.c65 pllm = data->pll_m - 1; in configure_mult_div()
77 bwadj = (data->pll_m - 1) >> 1; /* Divide pllm by 2 */ in configure_mult_div()
/rk3399_rockchip-uboot/arch/arm/mach-stm32/stm32f4/
H A Dclock.c85 u8 pll_m; member
117 .pll_m = 8,
128 .pll_m = 8,
167 writel(sys_pll_psc.pll_m in configure_clocks()
/rk3399_rockchip-uboot/tools/
H A Dublimage.h68 uint32_t pll_m; /* member
H A Dublimage.c104 ublhdr->pll_m = get_cfg_value(token, name, lineno); in parse_cfg_cmd()
/rk3399_rockchip-uboot/drivers/clk/
H A Dclk_stm32f7.c63 u8 pll_m; member
99 .pll_m = 25,
140 pllcfgr |= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT; in configure_clocks()
/rk3399_rockchip-uboot/arch/arm/mach-keystone/include/mach/
H A Dclock.h115 int pll_m; /* PLL Multiplier */ member
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Dnvidia,tegra20-car.txt150 119 pll_m