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/rk3399_rockchip-uboot/arch/arm/dts/
H A Dimx6ull.dtsi68 clocks = <&clks IMX6UL_CLK_ARM>,
69 <&clks IMX6UL_CLK_PLL2_BUS>,
70 <&clks IMX6UL_CLK_PLL2_PFD2>,
71 <&clks IMX6UL_CA7_SECONDARY_SEL>,
72 <&clks IMX6UL_CLK_STEP>,
73 <&clks IMX6UL_CLK_PLL1_SW>,
74 <&clks IMX6UL_CLK_PLL1_SYS>,
75 <&clks IMX6UL_PLL1_BYPASS>,
76 <&clks IMX6UL_CLK_PLL1>,
77 <&clks IMX6UL_PLL1_BYPASS_SRC>,
[all …]
H A Dimx6sx.dtsi76 clocks = <&clks IMX6SX_CLK_ARM>,
77 <&clks IMX6SX_CLK_PLL2_PFD2>,
78 <&clks IMX6SX_CLK_STEP>,
79 <&clks IMX6SX_CLK_PLL1_SW>,
80 <&clks IMX6SX_CLK_PLL1_SYS>;
149 clocks = <&clks IMX6SX_CLK_OCRAM>;
166 clocks = <&clks IMX6SX_CLK_GPU>,
167 <&clks IMX6SX_CLK_GPU>,
168 <&clks IMX6SX_CLK_GPU>;
182 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
[all …]
H A Dimx6sll.dtsi67 clocks = <&clks IMX6SLL_CLK_ARM>,
68 <&clks IMX6SLL_CLK_PLL2_PFD2>,
69 <&clks IMX6SLL_CLK_STEP>,
70 <&clks IMX6SLL_CLK_PLL1_SW>,
71 <&clks IMX6SLL_CLK_PLL1_SYS>,
72 <&clks IMX6SLL_CLK_PLL1>,
73 <&clks IMX6SLL_PLL1_BYPASS>,
74 <&clks IMX6SLL_PLL1_BYPASS_SRC>;
136 clocks = <&clks IMX6SLL_CLK_PLL2_PFD2>, <&clks IMX6SLL_CLK_PLL2_198M>,
137 <&clks IMX6SLL_CLK_PLL2_BUS>, <&clks IMX6SLL_CLK_ARM>,
[all …]
H A Dimx6qdl.dtsi91 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
102 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
103 <&clks IMX6QDL_CLK_GPMI_APB>,
104 <&clks IMX6QDL_CLK_GPMI_BCH>,
105 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
106 <&clks IMX6QDL_CLK_PER1_BCH>;
120 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
121 <&clks IMX6QDL_CLK_HDMI_ISFR>;
146 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
147 <&clks IMX6QDL_CLK_GPU3D_CORE>,
[all …]
H A Dimx6ul.dtsi73 clocks = <&clks IMX6UL_CLK_ARM>,
74 <&clks IMX6UL_CLK_PLL2_BUS>,
75 <&clks IMX6UL_CLK_PLL2_PFD2>,
76 <&clks IMX6UL_CA7_SECONDARY_SEL>,
77 <&clks IMX6UL_CLK_STEP>,
78 <&clks IMX6UL_CLK_PLL1_SW>,
79 <&clks IMX6UL_CLK_PLL1_SYS>,
80 <&clks IMX6UL_PLL1_BYPASS>,
81 <&clks IMX6UL_CLK_PLL1>,
82 <&clks IMX6UL_PLL1_BYPASS_SRC>,
[all …]
H A Dimx7ulp.dtsi159 clocks = <&clks IMX7ULP_CLK_DMA1>, <&clks IMX7ULP_CLK_DMA_MUX1>;
193 clocks = <&clks IMX7ULP_CLK_SNVS>;
201 clocks = <&clks IMX7ULP_CLK_LPTPM5>;
209 clocks = <&clks IMX7ULP_CLK_LPIT1>;
211 assigned-clocks = <&clks IMX7ULP_CLK_LPIT1>;
212 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
219 clocks = <&clks IMX7ULP_CLK_LPI2C4>;
221 assigned-clocks = <&clks IMX7ULP_CLK_LPI2C4>;
222 assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
231 clocks = <&clks IMX7ULP_CLK_LPI2C5>;
[all …]
H A Dimx6q.dtsi47 clocks = <&clks IMX6QDL_CLK_ARM>,
48 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
49 <&clks IMX6QDL_CLK_STEP>,
50 <&clks IMX6QDL_CLK_PLL1_SW>,
51 <&clks IMX6QDL_CLK_PLL1_SYS>;
85 clocks = <&clks IMX6QDL_CLK_OCRAM>;
96 clocks = <&clks IMX6Q_CLK_ECSPI5>,
97 <&clks IMX6Q_CLK_ECSPI5>;
114 clocks = <&clks IMX6QDL_CLK_SATA>,
115 <&clks IMX6QDL_CLK_SATA_REF_100M>,
[all …]
H A Dimx6sl.dtsi68 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
69 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
70 <&clks IMX6SL_CLK_PLL1_SYS>;
115 clocks = <&clks IMX6SL_CLK_OCRAM>;
155 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
156 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
157 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
158 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
159 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
174 clocks = <&clks IMX6SL_CLK_ECSPI1>,
[all …]
H A Dimx7s.dtsi100 clocks = <&clks IMX7D_CLK_ARM>;
128 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
160 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
173 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
210 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
237 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
251 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
413 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
420 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
428 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
[all …]
H A Dimx6dl.dtsi42 clocks = <&clks IMX6QDL_CLK_ARM>,
43 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
44 <&clks IMX6QDL_CLK_STEP>,
45 <&clks IMX6QDL_CLK_PLL1_SW>,
46 <&clks IMX6QDL_CLK_PLL1_SYS>;
66 clocks = <&clks IMX6QDL_CLK_OCRAM>;
97 clocks = <&clks IMX6DL_CLK_I2C4>;
123 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
124 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
125 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
H A Dimx53.dtsi53 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
54 <&clks IMX5_CLK_UART2_PER_GATE>;
61 clks: ccm@53fd4000{ label
90 clocks = <&clks IMX5_CLK_SDMA_GATE>,
91 <&clks IMX5_CLK_SDMA_GATE>;
102 clocks = <&clks IMX5_CLK_FEC_GATE>,
103 <&clks IMX5_CLK_FEC_GATE>,
104 <&clks IMX5_CLK_FEC_GATE>;
H A Dimx7d.dtsi77 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
94 clocks = <&clks IMX7D_USB_CTRL_CLK>;
109 clocks = <&clks IMX7D_USB_PHY2_CLK>;
119 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
120 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
121 <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
122 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
123 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
H A Dimx6qdl-logicpd.dtsi40 &clks {
41 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
42 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
43 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
44 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
H A Dimx6qdl-icore.dtsi73 &clks {
74 assigned-clocks = <&clks IMX6QDL_CLK_LVDS2_SEL>;
75 assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;
/rk3399_rockchip-uboot/drivers/clk/
H A Dclk_sandbox_test.c13 struct clk clks[SANDBOX_CLK_TEST_ID_COUNT]; member
30 &sbct->clks[i]); in sandbox_clk_test_get()
52 return clk_get_rate(&sbct->clks[id]); in sandbox_clk_test_get_rate()
62 return clk_set_rate(&sbct->clks[id], rate); in sandbox_clk_test_set_rate()
72 return clk_enable(&sbct->clks[id]); in sandbox_clk_test_enable()
89 return clk_disable(&sbct->clks[id]); in sandbox_clk_test_disable()
105 ret = clk_free(&sbct->clks[i]); in sandbox_clk_test_free()
126 if (!clk_valid(&sbct->clks[i])) in sandbox_clk_test_valid()
H A Dclk-uclass.c118 bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL); in clk_get_bulk()
119 if (!bulk->clks) in clk_get_bulk()
123 ret = clk_get_by_index(dev, i, &bulk->clks[i]); in clk_get_bulk()
133 err = clk_release_all(bulk->clks, bulk->count); in clk_get_bulk()
399 ret = clk_enable(&bulk->clks[i]); in clk_enable_bulk()
424 ret = clk_disable(&bulk->clks[i]); in clk_disable_bulk()
/rk3399_rockchip-uboot/drivers/usb/host/
H A Ddwc3-of-simple.c22 struct clk_bulk clks; member
51 ret = clk_get_bulk(dev, &simple->clks); in dwc3_of_simple_clk_init()
58 ret = clk_enable_bulk(&simple->clks); in dwc3_of_simple_clk_init()
60 clk_release_bulk(&simple->clks); in dwc3_of_simple_clk_init()
90 clk_release_bulk(&simple->clks); in dwc3_of_simple_remove()
/rk3399_rockchip-uboot/drivers/ddr/fsl/
H A Dutil.c88 unsigned long long clks, clks_rem; in picos_to_mclk() local
96 clks = picos * (unsigned long long)data_rate; in picos_to_mclk()
101 clks_rem = do_div(clks, UL_5POW12); in picos_to_mclk()
102 clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12; in picos_to_mclk()
103 clks >>= 13; in picos_to_mclk()
107 clks++; in picos_to_mclk()
110 if (clks > ULL_8FS) in picos_to_mclk()
111 clks = ULL_8FS; in picos_to_mclk()
112 return (unsigned int) clks; in picos_to_mclk()
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3288/
H A Drk3288.c298 } clks[] = { in do_clock() local
319 for (i = 0; i < ARRAY_SIZE(clks); i++) { in do_clock()
323 clk.id = clks[i].id; in do_clock()
329 printf("%s: %lu\n", clks[i].name, rate); in do_clock()
/rk3399_rockchip-uboot/drivers/phy/
H A Dphy-rockchip-snps-pcie3.c49 struct clk_bulk clks; member
183 ret = clk_enable_bulk(&priv->clks); in rochchip_p3phy_init()
195 clk_disable_bulk(&priv->clks); in rochchip_p3phy_init()
208 clk_disable_bulk(&priv->clks); in rochchip_p3phy_exit()
/rk3399_rockchip-uboot/include/
H A Dclk.h76 struct clk *clks; member
202 return clk_release_all(bulk->clks, bulk->count); in clk_release_bulk()
/rk3399_rockchip-uboot/drivers/usb/dwc3/
H A Ddwc3-generic.h17 struct clk_bulk clks; member
H A Ddwc3-generic.c408 ret = clk_get_bulk(dev, &glue->clks); in dwc3_glue_clk_init()
415 ret = clk_enable_bulk(&glue->clks); in dwc3_glue_clk_init()
417 clk_release_bulk(&glue->clks); in dwc3_glue_clk_init()
447 if (glue->clks.count == 0) { in dwc3_glue_probe()
478 clk_release_bulk(&glue->clks); in dwc3_glue_remove()
/rk3399_rockchip-uboot/drivers/pwm/
H A Drk_pwm.c277 struct clk_bulk clks = { 0 }; in rk_pwm_clk_init() local
280 ret = clk_get_bulk(dev, &clks); in rk_pwm_clk_init()
288 ret = clk_enable_bulk(&clks); in rk_pwm_clk_init()
291 clk_release_bulk(&clks); in rk_pwm_clk_init()
/rk3399_rockchip-uboot/drivers/usb/gadget/
H A Ddwc2_udc_otg.c946 struct clk_bulk clks; member
1127 struct clk_bulk *clks) in dwc2_udc_otg_clk_init() argument
1131 ret = clk_get_bulk(dev, clks); in dwc2_udc_otg_clk_init()
1138 ret = clk_enable_bulk(clks); in dwc2_udc_otg_clk_init()
1140 clk_release_bulk(clks); in dwc2_udc_otg_clk_init()
1155 ret = dwc2_udc_otg_clk_init(dev, &priv->clks); in dwc2_udc_otg_probe()
1211 clk_release_bulk(&priv->clks); in dwc2_udc_otg_remove()

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