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/rk3399_rockchip-uboot/arch/arm/dts/
H A Dexynos4412-odroid.dts46 regulator-name = "VDD_ALIVE_1.0V";
52 regulator-name = "VDDQ_VM1M2_1.2V";
64 regulator-name = "VDDQ_MMC2_2.8V";
70 regulator-name = "VDDQ_MMC0/1/3_1.8V";
76 regulator-name = "VMPLL_1.0V";
82 regulator-name = "VPLL_1.1V";
88 regulator-name = "VDD_MIPI/HDMI_1.0V";
94 regulator-name = "VDD_MIPI/HDMI_1.8V";
100 regulator-name = "VDD_ABB1_1.8V";
106 regulator-name = "VDD_UOTG_3.0V";
[all …]
H A Ds5pc1xx-goni.dts52 regulator-name = "VALIVE_1.1V";
60 regulator-name = "VUSB+MIPI_1.1V";
68 regulator-name = "VADC_3.3V";
75 regulator-name = "VTF_2.8V";
82 regulator-name = "VCC_3.3V";
89 regulator-name = "VLCD_1.8V";
97 regulator-name = "VUSB+VDAC_3.3V";
104 regulator-name = "VCC+VCAM_2.8V";
111 regulator-name = "VPLL_1.1V";
119 regulator-name = "CAM_IO_2.8V";
[all …]
H A Dexynos4210-universal_c210.dts85 regulator-name = "VALIVE_1.2V";
92 regulator-name = "VUSB+MIPI_1.1V";
99 regulator-name = "VADC_3.3V";
105 regulator-name = "VTF_2.8V";
117 regulator-name = "VLCD+VMIPI_1.8V";
123 regulator-name = "VUSB+VDAC_3.3V";
130 regulator-name = "VCC_2.8V";
137 regulator-name = "VPLL_1.1V";
145 regulator-name = "CAM_AF_3.3V";
151 regulator-name = "PS_2.8V";
[all …]
H A Dexynos4412-trats2.dts132 regulator-name = "VMIPI_1.0V";
140 regulator-name = "CAM_ISP_MIPI_1.2V";
148 regulator-name = "VMIPI_1.8V";
156 regulator-name = "VABB1_1.95V";
165 regulator-name = "VUOTG_3.0V";
173 regulator-name = "NFC_AVDD_1.8V";
181 regulator-name = "VABB2_1.95V";
190 regulator-name = "VHSIC_1.0V";
198 regulator-name = "VHSIC_1.8V";
206 regulator-name = "CAM_SENSOR_CORE_1.2V";
[all …]
H A Dexynos4210-trats.dts123 regulator-name = "VMIPI_1.8V";
136 regulator-name = "CAM_ISP_1.8V";
162 regulator-name = "VT_CAM_1.8V";
174 regulator-name = "VLCD_2.2V";
180 regulator-name = "CAM_SENSOR_IO_1.8V";
186 regulator-name = "VDDQ_M1M2_1.2V";
212 regulator-name = "CAM_ISP_CORE_1.2V";
225 regulator-name = "VCC_SUB_2.0V";
H A Dsocfpga_arria5_socdk.dts10 model = "Altera SOCFPGA Arria V SoC Development Kit";
33 regulator-name = "3.3V";
H A Dsocfpga_cyclone5_is1.dts10 model = "SoCFPGA Cyclone V IS1";
30 regulator-name = "3.3V";
H A Dsocfpga_cyclone5_socdk.dts10 model = "Altera SOCFPGA Cyclone V SoC Development Kit";
33 regulator-name = "3.3V";
H A Dtegra20-trimslice.dts49 nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
107 gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
/rk3399_rockchip-uboot/arch/arm/mach-socfpga/
H A DKconfig61 bool "Altera SOCFPGA SoCDK (Arria V)"
65 bool "Altera SOCFPGA SoCDK (Cyclone V)"
69 bool "Aries MCVEVK (Cyclone V)"
73 bool "EBV SoCrates (Cyclone V)"
77 bool "IS1 (Cyclone V)"
81 bool "samtec VIN|ING FPGA (Cyclone V)"
86 bool "SR1500 (Cyclone V)"
90 bool "Terasic DE0-Nano-Atlas (Cyclone V)"
94 bool "Terasic DE10-Nano (Cyclone V)"
98 bool "Terasic DE1-SoC (Cyclone V)"
[all …]
/rk3399_rockchip-uboot/drivers/power/
H A DKconfig109 generic 3.3V IO voltage for external devices like the lcd-panal and
110 sdcard interfaces, etc. On most boards dcdc1 is undervolted to 3.0V to
126 On A10(s) / A13 / A20 boards dcdc2 is VDD-CPU and should be 1.4V.
127 On A31 boards dcdc2 is used for VDD-GPU and should be 1.2V.
128 On A23/A33 boards dcdc2 is used for VDD-SYS and should be 1.1V.
130 On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V.
131 On R40 boards dcdc2 is VDD-CPU and should be 1.1V
145 should be 1.25V.
146 On A10s boards with an axp152 dcdc3 is VCC-DRAM and should be 1.5V.
147 On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V.
[all …]
/rk3399_rockchip-uboot/arch/sandbox/dts/
H A Dsandbox_pmic.dtsi50 regulator-name = "SUPPLY_1.2V";
59 regulator-name = "SUPPLY_3.3V";
65 regulator-name = "VDD_EMMC_1.8V";
74 regulator-name = "VDD_LCD_3.3V";
80 regulator-name = "buck_SUPPLY_1.5V";
/rk3399_rockchip-uboot/board/freescale/ls1012afrdm/
H A DREADME19 operating at 1.35 V
42 - 5 V input supply from USB
43 - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and
/rk3399_rockchip-uboot/board/toradex/colibri_t20/
H A Dcolibri_t20.c127 gpio_request(TEGRA_GPIO(V, 4), "LAN_RESET"); in pin_mux_usb()
128 gpio_direction_output(TEGRA_GPIO(V, 4), 0); in pin_mux_usb()
131 gpio_set_value(TEGRA_GPIO(V, 4), 1); in pin_mux_usb()
/rk3399_rockchip-uboot/board/avionic-design/common/
H A Dtamonten-ng.c45 gpio_request(TEGRA_GPIO(V, 2), "ALIVE"); in gpio_early_init()
46 gpio_direction_output(TEGRA_GPIO(V, 2), 1); in gpio_early_init()
/rk3399_rockchip-uboot/board/freescale/mx28evk/
H A DREADME22 * Wall 5V: Up
23 * VDD 5V: To the left (off)
31 * Wall 5V: Up
32 * VDD 5V: To the left (off)
/rk3399_rockchip-uboot/doc/device-tree-bindings/regulator/
H A Dmax77686.txt28 regulator-name = "VDD_ALIVE_1.0V";
36 regulator-name = "VDDQ_VM1M2_1.2V";
55 regulator-name = "VDD_MIF_1.0V";
H A Dsandbox.txt32 regulator-name = "VDD_1.0V";
41 regulator-name = "VDD_1.8V";
/rk3399_rockchip-uboot/board/freescale/ls1021aiot/
H A DREADME11 - DDR power supplies 1.35V to all devices with
23 - 12V@5A DC
/rk3399_rockchip-uboot/doc/device-tree-bindings/adc/
H A Dadc.txt38 | (3.3V)| _|VSSref |
47 regulator-name = "SUPPLY_3.3V";
/rk3399_rockchip-uboot/scripts/
H A Dmkmakefile34 VERBOSE := \$(V)
/rk3399_rockchip-uboot/board/freescale/t4qds/
H A DREADME29 DDR power supplies 1.5V to all devices with automatic tracking of VTT.
30 Power software-switchable to 1.35V if software detects all DDR3LP devices.
53 Collects V-I-T data in background for code/power profiling.
66 - Adjustable from (0.7V to 1.3V at 80A
68 Dedicated regulator for GVDD_PL: 1.35/1.5V at 22A
/rk3399_rockchip-uboot/board/freescale/mpc8641hpcn/
H A DREADME43 SW3(1-7) = 0011000 CONFIG_SYS_VID = 0011000 :: VCORE = 1.2V
44 0100000 :: VCORE = 1.11V
45 SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V
46 1 :: VCC_PLAT = 1.0V
/rk3399_rockchip-uboot/board/freescale/mpc837xerdb/
H A DREADME17 G) 1 32-bit, 3.3 V, PCI slot
18 H) 1 32-bit, 3.3 V, Mini-PCI slot
/rk3399_rockchip-uboot/arch/arm/cpu/arm1136/
H A Du-boot-spl.lds7 * Aneesh V <aneesh@ti.com>

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