Home
last modified time | relevance | path

Searched refs:CWL (Results 1 – 1 of 1) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c93 u32 CWL; member
364 u32 CWL = 0; in mctl_channel_init() local
441 CWL = para->cl_cwl_table[i].CWL; in mctl_channel_init()
443 debug("found CL/CWL: CL = %d, CWL = %d\n", CL, CWL); in mctl_channel_init()
448 if ((CL == 0) && (CWL == 0)) { in mctl_channel_init()
466 mr[2] = DDR3_MR2_TWL(CWL); in mctl_channel_init()
521 #define WR2PRE (MCTL_BL/2 + CWL + tWTR) in mctl_channel_init()
523 #define WR2RD (MCTL_BL/2 + CWL + tWTR) in mctl_channel_init()
528 #define RD2WR (CL + MCTL_BL/2 + 2 - CWL) in mctl_channel_init()
542 writel((MCTL_DIV2(CWL) << 24) | (MCTL_DIV2(CL) << 16) | in mctl_channel_init()
[all …]