Searched refs:CLK_V0PLL_DIV (Results 1 – 2 of 2) sorted by relevance
106 RK3506_CLK_DUMP(CLK_V0PLL_DIV, "clk_v0pll_div"),287 case CLK_V0PLL_DIV: in rk3506_pll_div_get_rate()323 case CLK_V0PLL_DIV: in rk3506_pll_div_set_rate()1043 case CLK_V0PLL_DIV: in rk3506_clk_get_rate()1119 case CLK_V0PLL_DIV: in rk3506_clk_set_rate()1208 priv->v0pll_div_hz = rk3506_pll_div_get_rate(priv, CLK_V0PLL_DIV); in rk3506_clk_init()
24 #define CLK_V0PLL_DIV 23 macro