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Searched refs:CLK_GPLL_DIV (Results 1 – 2 of 2) sorted by relevance

/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3506.c104 RK3506_CLK_DUMP(CLK_GPLL_DIV, "clk_gpll_div"),
277 case CLK_GPLL_DIV: in rk3506_pll_div_get_rate()
311 case CLK_GPLL_DIV: in rk3506_pll_div_set_rate()
1041 case CLK_GPLL_DIV: in rk3506_clk_get_rate()
1117 case CLK_GPLL_DIV: in rk3506_clk_set_rate()
1200 priv->gpll_div_hz = rk3506_pll_div_get_rate(priv, CLK_GPLL_DIV); in rk3506_clk_init()
/rk3399_rockchip-uboot/include/dt-bindings/clock/
H A Drockchip,rk3506-cru.h22 #define CLK_GPLL_DIV 21 macro