Searched refs:CGU_CLK_GPLL (Results 1 – 2 of 2) sorted by relevance
78 } else if (id == CGU_CLK_GPLL) { in rk628_cru_clk_get_rate_pll()152 else if (id == CGU_CLK_GPLL) in rk628_cru_clk_set_rate_pll()284 parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_GPLL); in rk628_cru_clk_set_rate_sclk_vop()305 parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_GPLL); in rk628_cru_clk_get_rate_sclk_vop()326 parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_GPLL); in rk628_cru_clk_get_rate_clk_imodet()347 parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_GPLL); in rk628_cru_clk_set_rate_rx_read()367 parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_GPLL); in rk628_cru_clk_get_rate_uart_src()415 parent_rate = rk628_cru_clk_set_rate_pll(rk628, CGU_CLK_GPLL, rate*4); in rk628_cru_clk_set_rate_sclk_hdmirx_aud()446 parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_GPLL); in rk628_cru_clk_get_rate_sclk_hdmirx_aud()461 parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_GPLL); in rk628_cru_clk_get_rate_bt1120_dec_parent()[all …]
137 #define CGU_CLK_GPLL 2 macro