Home
last modified time | relevance | path

Searched refs:t_rp (Results 1 – 3 of 3) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_memory_controller.c179 t_rtp, t_rp, t_rcd, rd_latency, tw_rin_clk_cycles, in configure_ddr_sched_ctrl_regs() local
229 t_rp = PCH_TO_VALID(data); in configure_ddr_sched_ctrl_regs()
259 rd_to_miss = t_rtp + t_rp + t_rcd - burst_len_sched_clk; in configure_ddr_sched_ctrl_regs()
261 / 2) - rd_to_wr + t_rp + t_rcd; in configure_ddr_sched_ctrl_regs()
/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_memory_controller.c178 t_rtp, t_rp, t_rcd, rd_latency, tw_rin_clk_cycles, in configure_ddr_sched_ctrl_regs() local
228 t_rp = PCH_TO_VALID(data); in configure_ddr_sched_ctrl_regs()
258 rd_to_miss = t_rtp + t_rp + t_rcd - burst_len_sched_clk; in configure_ddr_sched_ctrl_regs()
260 / 2) - rd_to_wr + t_rp + t_rcd; in configure_ddr_sched_ctrl_regs()
/rk3399_ARM-atf/plat/intel/soc/stratix10/soc/
H A Ds10_memory_controller.c207 t_rtp, t_rp, t_rcd, rd_latency, tw_rin_clk_cycles, in configure_ddr_sched_ctrl_regs() local
257 t_rp = PCH_TO_VALID(data); in configure_ddr_sched_ctrl_regs()
287 rd_to_miss = t_rtp + t_rp + t_rcd - burst_len_sched_clk; in configure_ddr_sched_ctrl_regs()
289 / 2) - rd_to_wr + t_rp + t_rcd; in configure_ddr_sched_ctrl_regs()