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Searched refs:pw (Results 1 – 7 of 7) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_pmic_wrap.c84 static struct pmic_wrap_setting *pw; variable
103 pw = &pw57; in _mt_spm_pmic_table_init()
105 pw = &pw66; in _mt_spm_pmic_table_init()
108 memcpy(pw->addr, pwrap_cmd_default, sizeof(pwrap_cmd_default)); in _mt_spm_pmic_table_init()
116 if (pw == NULL || pw->addr[0].cmd_addr == 0) { in mt_spm_pmic_wrap_set_phase()
120 if (pw->phase != phase) { in mt_spm_pmic_wrap_set_phase()
121 pw->phase = phase; in mt_spm_pmic_wrap_set_phase()
125 for (idx = 0; idx < pw->set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
126 addr = pw->set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
127 data = pw->set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm_pmic_wrap.c52 static struct pmic_wrap_setting pw = { variable
97 memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default)); in _mt_spm_pmic_table_init()
108 if (pw.phase == phase) { in mt_spm_pmic_wrap_set_phase()
112 if (pw.addr[0].cmd_addr == 0UL) { in mt_spm_pmic_wrap_set_phase()
116 pw.phase = phase; in mt_spm_pmic_wrap_set_phase()
119 for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
120 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
121 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
122 mmio_write_32(pw.addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
135 if (idx >= pw.set[phase].nr_idx) { in mt_spm_pmic_wrap_set_cmd()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/
H A Dmt_spm_pmic_wrap.c57 static struct pmic_wrap_setting pw = { variable
102 memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default)); in _mt_spm_pmic_table_init()
109 if ((phase >= NR_PMIC_WRAP_PHASE) || (pw.phase == phase)) { in mt_spm_pmic_wrap_set_phase()
113 if (pw.addr[0].cmd_addr == 0) { in mt_spm_pmic_wrap_set_phase()
117 pw.phase = phase; in mt_spm_pmic_wrap_set_phase()
120 for (idx = 0; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
121 mmio_write_32(pw.addr[idx].cmd_addr, in mt_spm_pmic_wrap_set_phase()
122 (pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT) | in mt_spm_pmic_wrap_set_phase()
123 (pw.set[phase]._[idx].cmd_wdata)); in mt_spm_pmic_wrap_set_phase()
131 if ((phase >= NR_PMIC_WRAP_PHASE) || (idx >= pw.set[phase].nr_idx)) { in mt_spm_pmic_wrap_set_cmd()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_pmic_wrap.c52 static struct pmic_wrap_setting pw = { variable
97 memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default)); in _mt_spm_pmic_table_init()
108 if (pw.phase == phase) { in mt_spm_pmic_wrap_set_phase()
112 if (pw.addr[0].cmd_addr == 0UL) { in mt_spm_pmic_wrap_set_phase()
116 pw.phase = phase; in mt_spm_pmic_wrap_set_phase()
119 for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
120 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
121 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
122 mmio_write_32(pw.addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
135 if (idx >= pw.set[phase].nr_idx) { in mt_spm_pmic_wrap_set_cmd()
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/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spm/
H A Dspm_pmic_wrap.c55 static struct pmic_wrap_setting pw = { variable
112 memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default)); in _mt_spm_pmic_table_init()
122 if (pw.phase == phase) in mt_spm_pmic_wrap_set_phase()
125 if (pw.addr[0].cmd_addr == 0) in mt_spm_pmic_wrap_set_phase()
128 pw.phase = phase; in mt_spm_pmic_wrap_set_phase()
132 for (idx = 0; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
133 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
134 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
135 mmio_write_32(pw.addr[idx].cmd_addr, addr | data); in mt_spm_pmic_wrap_set_phase()
147 if (idx >= pw.set[phase].nr_idx) in mt_spm_pmic_wrap_set_cmd()
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/rk3399_ARM-atf/plat/mediatek/drivers/spm/version/pmic_wrap/v1/
H A Dmt_spm_pmic_wrap.c79 void mt_spm_pmic_wrap_set_table(struct pmic_wrap_setting *pw) in mt_spm_pmic_wrap_set_table() argument
81 pmic_wrap = pw; in mt_spm_pmic_wrap_set_table()
/rk3399_ARM-atf/plat/mediatek/drivers/spm/version/pmic_wrap/inc/
H A Dmt_spm_pmic_wrap.h30 void mt_spm_pmic_wrap_set_table(struct pmic_wrap_setting *pw);