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Searched refs:pll_cfg_set (Results 1 – 1 of 1) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_clock_manager.c20 static const pll_cfg_t pll_cfg_set[] = { variable
211 for (uint32_t i = 0; i < ARRAY_SIZE(pll_cfg_set); i++) { in config_pll_pd_state()
212 (void)pll_source_sync_read(pll_type, pll_cfg_set[i].addr, &rdata, in config_pll_pd_state()
215 (void)pll_source_sync_config(pll_type, pll_cfg_set[i].addr, in config_pll_pd_state()
216 ((rdata & ~pll_cfg_set[i].mask) | pll_cfg_set[i].data), in config_pll_pd_state()