Searched refs:num_entries (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/plat/arm/board/neoverse_rd/common/ |
| H A D | nrd_image_load.c | 25 uint64_t num_entries; /* Number of entries in the list */ member
41 SDS_ISOLATED_CPU_LIST_ID, 0, &list->num_entries, in plat_arm_nrd_get_isolated_cpu_list()
42 sizeof(list->num_entries), SDS_ACCESS_MODE_CACHED); in plat_arm_nrd_get_isolated_cpu_list()
45 list->num_entries = 0; in plat_arm_nrd_get_isolated_cpu_list()
49 if (list->num_entries > PLATFORM_CORE_COUNT) { in plat_arm_nrd_get_isolated_cpu_list()
52 list->num_entries, PLATFORM_CORE_COUNT); in plat_arm_nrd_get_isolated_cpu_list()
54 } else if (list->num_entries == 0) { in plat_arm_nrd_get_isolated_cpu_list()
61 sizeof(list->num_entries), in plat_arm_nrd_get_isolated_cpu_list()
63 sizeof(list->mpid_list[0]) * list->num_entries, in plat_arm_nrd_get_isolated_cpu_list()
129 if (cpu_mpid_list.num_entries > 0) { in plat_nrd_append_config_node()
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| /rk3399_ARM-atf/plat/nvidia/tegra/drivers/memctrl/ |
| H A D | memctrl_v2.c | 121 uint32_t i, num_entries = 0; in tegra_mc_save_context() local
138 while (mc_ctx_regs[num_entries].reg != 0xFFFFFFFFU) { in tegra_mc_save_context()
139 num_entries++; in tegra_mc_save_context()
143 if (num_entries != mc_ctx_regs[0].val) { in tegra_mc_save_context()
149 for (i = 1U; i < num_entries; i++) { in tegra_mc_save_context()
154 num_entries++; in tegra_mc_save_context()
158 sizeof(mc_regs_t) * num_entries); in tegra_mc_save_context()
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| /rk3399_ARM-atf/plat/xilinx/common/ |
| H A D | plat_startup.c | 207 handoff_addr, HandoffParams->num_entries); in xbl_handover()
208 if (HandoffParams->num_entries > XBL_MAX_PARTITIONS) { in xbl_handover()
210 HandoffParams->num_entries, XBL_MAX_PARTITIONS); in xbl_handover()
220 for (size_t i = 0; i < HandoffParams->num_entries; i++) { in xbl_handover()
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| /rk3399_ARM-atf/plat/xilinx/common/include/ |
| H A D | plat_startup.h | 32 uint32_t num_entries; member
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