Searched refs:iface (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/plat/marvell/armada/common/ |
| H A D | marvell_ddr_info.c | 15 #define DRAM_CH0_MMAP_LOW_REG(iface, cs, base) \ argument
16 (base + DRAM_CH0_MMAP_LOW_OFFSET + (iface) * 0x10000 + (cs) * 0x8)
17 #define DRAM_CH0_MMAP_HIGH_REG(iface, cs, base) \ argument
18 (DRAM_CH0_MMAP_LOW_REG(iface, cs, base) + 4)
29 #define DRAM_CS_ENABLED(iface, cs, base) \ argument
30 (mmio_read_32(DRAM_CH0_MMAP_LOW_REG(iface, cs, base)) & \
32 #define GET_DRAM_REGION_SIZE_CODE(iface, cs, base) \ argument
33 (mmio_read_32(DRAM_CH0_MMAP_LOW_REG(iface, cs, base)) & \
81 uint8_t cs, iface; in mvebu_get_dram_size() local
83 for (iface = 0; iface < DRAM_MAX_IFACE; iface++) { in mvebu_get_dram_size()
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| /rk3399_ARM-atf/plat/intel/soc/agilex5/soc/ |
| H A D | agilex5_iossm_mailbox.c | 301 int iface; in trig_mem_cal() local
311 for (iface = 0; iface < 2; iface++) { in trig_mem_cal()
333 uint32_t resp = mmio_read_32(base + (iface == 0 ? in trig_mem_cal()
353 (inst_ctrl->mb_ctrl.ip_instance_id[iface] << 24) | in trig_mem_cal()
354 (inst_ctrl->mb_ctrl.ip_type[iface] << 29); in trig_mem_cal()
377 resp = mmio_read_32(base + (iface == 0 ? in trig_mem_cal()
390 inst, iface); in trig_mem_cal()
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