Searched refs:hold_base (Results 1 – 7 of 7) sorted by relevance
35 uint64_t hold_base[PLATFORM_CORE_COUNT]; variable54 hold_base[pos] = PLAT_FPGA_HOLD_STATE_GO; in fpga_pwr_domain_on()55 flush_dcache_range((uintptr_t)&hold_base[pos], sizeof(uint64_t)); in fpga_pwr_domain_on()
150 uintptr_t hold_base = PLAT_RPI3_TM_HOLD_BASE; in rpi3_pwr_domain_on() local154 hold_base += pos * PLAT_RPI3_TM_HOLD_ENTRY_SIZE; in rpi3_pwr_domain_on()156 mmio_write_64(hold_base, PLAT_RPI3_TM_HOLD_STATE_GO); in rpi3_pwr_domain_on()187 uintptr_t hold_base = PLAT_RPI3_TM_HOLD_BASE; in rpi3_pwr_down_wfi() local198 mmio_write_64(hold_base, PLAT_RPI3_TM_HOLD_STATE_BSP_OFF); in rpi3_pwr_down_wfi()
19 uint64_t *hold_base = (uint64_t *)A5DS_HOLD_BASE; in a5ds_pwr_domain_on() local21 hold_base[pos] = A5DS_HOLD_STATE_GO; in a5ds_pwr_domain_on()
141 uintptr_t hold_base = PLAT_NPCM_TM_HOLD_BASE; in npcm845x_pwr_domain_on() local145 hold_base += pos * PLAT_NPCM_TM_HOLD_ENTRY_SIZE; in npcm845x_pwr_domain_on()147 mmio_write_64(hold_base, PLAT_NPCM_TM_HOLD_STATE_GO); in npcm845x_pwr_domain_on()335 uintptr_t hold_base = PLAT_NPCM_TM_HOLD_BASE; in npcm845x_pwr_down_wfi() local346 mmio_write_64(hold_base, PLAT_NPCM_TM_HOLD_STATE_BSP_OFF); in npcm845x_pwr_down_wfi()
136 uint64_t *hold_base = (uint64_t *)PLAT_QEMU_HOLD_BASE; in qemu_pwr_domain_on() local142 hold_base[pos] = PLAT_QEMU_HOLD_STATE_GO; in qemu_pwr_domain_on()
128 uint64_t *hold_base = (uint64_t *)PLAT_QEMU_HOLD_BASE; in qemu_pwr_domain_on() local130 hold_base[pos] = PLAT_QEMU_HOLD_STATE_GO; in qemu_pwr_domain_on()
77 adrp x1, hold_base78 add x1, x1, :lo12:hold_base