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/rk3399_ARM-atf/lib/zlib/
H A Dinflate.c449 have = strm->avail_in; \
460 strm->avail_in = have; \
476 if (have == 0) goto inf_leave; \
477 have--; \
594 unsigned have, left; /* available input and output */ in inflate() local
617 in = have; in inflate()
728 if (copy > have) copy = have; in inflate()
740 have -= copy; in inflate()
751 if (have == 0) goto inf_leave; in inflate()
759 } while (len && copy < have); in inflate()
[all …]
H A Dinflate.h118 unsigned have; /* number of code lengths in lens[] */ member
H A Dzlib.h1857 unsigned have; member
1865 ((g)->have ? ((g)->have--, (g)->pos++, *((g)->next)++) : (gzgetc)(g))
1868 ((g)->have ? ((g)->have--, (g)->pos++, *((g)->next)++) : (gzgetc)(g))
/rk3399_ARM-atf/
H A Ddco.txt18 have the right to submit it under the open source license
23 license and I have the right under that license to submit that
30 person who certified (a), (b) or (c) and I have not modified
/rk3399_ARM-atf/docs/plat/
H A Dnvidia-tegra.rst25 including legacy ARMv7 applications. The Denver 2 processors each have 128 KB
26 Instruction and 64 KB Data Level 1 caches; and have a 2MB shared Level 2
27 unified cache. The Cortex-A57 processors each have 48 KB Instruction and 32 KB
28 Data Level 1 caches; and also have a 2 MB shared Level 2 unified cache. A
63 including legacy Armv7-A applications. The Cortex-A57 processors each have
64 48 KB Instruction and 32 KB Data Level 1 caches; and have a 2 MB shared
65 Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction
66 and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache.
100 the scatter file to be used. Tegra platforms have verified BL31 image generation
H A Dindex.rst63 currently have associated documentation:
H A Drpi4.rst10 as well, but have not been tested at this point.
29 ``config.txt``. You should have AArch64 code in the file loaded as the
73 memory. The load addresses have a default, but can also be changed by
/rk3399_ARM-atf/docs/threat_model/firmware_threat_model/
H A Dindex.rst19 features within the project, we have not reached that point yet. We expect
23 data flow diagram, as well as a list of threats we have identified using the
/rk3399_ARM-atf/docs/design/
H A Dpsci-pd-tree.rst54 ``plat_get_aff_count()`` and ``plat_get_aff_state()`` have been
59 where the power domain tree does not have a single root node, for example,
74 above text further. The leaf and non-leaf nodes in this tree have been numbered
132 platform API have changed since it is required to validate the passed MPIDR. It
156 contiguous or certain cores have been disabled. This essentially means that the
157 MPIDRs have been sparsely allocated, that is, the size of the range of MPIDRs
178 To fulfill requirement 3 and 4, separate data structures have been defined
200 * -> cpu_start_idx + ncpus' have this node as their parent.
243 node. Other fields have been ignored for simplicity.
/rk3399_ARM-atf/docs/about/
H A Dcontact.rst8 If you think you have found a security vulnerability, please report this using
45 Arm licensees have an additional support conduit - they may contact Arm directly
H A Dlts.rst38 when a product is released, the companies have to support that in-market product
52 This means that companies have to maintain and backport critical updates to
66 We must have an objective criterion for selecting patches to be backported to
94 tends to have less churn and longer lifetime than a HLOS, TF-A is trying to
102 Given that many products that have a release cycle, have a yearly release
103 cycle, it would make sense to have yearly TF-A releases.
114 the basis for LTS then developers will have little time -- about a month,
257 down steps and does not have to make policy level decisions for merge, testing,
289 #. Some dependency patches, not listed in the CSV file, may have to be taken, to ease the
311 dedicated scripts for each LTS version which have to be updated manually. This is the case
[all …]
/rk3399_ARM-atf/docs/design_documents/
H A Dcmake_framework.rst92 generation or dtc for device tree compilation. These tools have to be found
104 In the provisioning phase, first we have to obtain the necessary resources, i.e.
105 clone the code repository and other dependencies. Next we have to do the
114 Usually during development only the steps in this second phase have to be
127 it. This means that all source and header files used by the target will have all
/rk3399_ARM-atf/docs/process/
H A Dcode-review-guidelines.rst54 to different timescales, and have different priorities. Keep this in
86 - If there is only one code owner and they have become unresponsive, ask one
94 directory to have the freedom to change it in any way. This way, your changes
109 There are no good or bad review comments. If you have any doubt about a patch or
157 through the ``Code-Owner-Review+1`` label in Gerrit. If instead, they have
207 - New files must have the correct license and copyright headers. See :ref:`this
232 - Before merging a patch, verify that all review comments have been addressed.
237 through the ``Maintainer-Review+1`` label in Gerrit. If instead, they have
H A Dfaq.rst24 they follow the coding guidelines, have already had some code review, and have
48 time. In simple cases where all potential regressions have already been tested,
H A Dsecurity.rst22 If you think you have found a security vulnerability, please **do not**
27 TF-A have a chance to consider the implications of the vulnerability and its
H A Dcommit-style.rst18 - What impact does it have?
104 does not yet have a designated scope, please add one.
141 Ensure that each commit also has a unique ``Change-Id:`` line. If you have
H A Dcontributing.rst7 - Make sure you have a Github account and you are logged on to
10 Also make sure that you have registered your full name and email address in
44 - Avoid long commit series. If you do have a long series, consider whether
70 should have a copyright notice and BSD-3-Clause SPDX license identifier of
222 New source files have been identified in your patch..
263 - In this case for ``Hikey`` boards additional build flags have been included
273 We have CI jobs which run a set of test configurations on every TF-A patch
H A Dmaintenance.rst41 #. Send an email to all existing TF-A maintainers, asking whether they have any
/rk3399_ARM-atf/docs/plat/marvell/armada/misc/
H A Dmvebu-io-win.rst8 Transactions that are decoded by CCU windows as IO peripheral, have an additional
/rk3399_ARM-atf/docs/plat/arm/fvp/
H A Dfvp-support.rst10 FVP_TC4) have their own dedicated TF-A platforms and will not work with this one.
95 All the above platforms have been tested with `Linaro Release 20.01`_.
/rk3399_ARM-atf/docs/getting_started/
H A Dimage-terminology.rst10 - Some of the names and abbreviated names have changed to accommodate new
95 have additional images and/or a different load/execution ordering. The
141 The terminology for these images has not been widely adopted yet but they have
181 Some systems may have additional processors to the AP and SCP. For example, a
/rk3399_ARM-atf/docs/
H A Dindex.rst79 have additional documentation that has been provided by the maintainers of the
86 have previously been raised against the software.
/rk3399_ARM-atf/docs/threat_model/
H A Dsupply_chain_threat_model.rst248 | | patches they have submitted. To achieve the commit the |
252 | Mitigations | We have not disallowed self-review/merge of patches |
290 | | patches they have submitted. To achieve the commit the |
311 | | not have maintainer review or merging privileges, |
322 | | vulnerability by itself may have a low impact but can |
323 | | have a major impact if used in combination with other |
537 | | malicious toolchains. Similar attacks have been used in |
547 | implemented?| toolchains, but have not yet provided scripts to |
562 | impact | exposed to malicious dependencies that have been missed |
636 | | | would have to | |
/rk3399_ARM-atf/docs/components/
H A Dcontext-management-library.rst33 security states (Non-Secure, Secure, Realm). Each world must have its
46 In general, an ideal trusted system should have Secure world-specific configurations
68 can have four distinct worlds (Non-Secure, Secure, Realm, Root).
86 Each world (Non-Secure, Secure, and Realm) should have their separate component
88 Both the Secure and Realm world have associated dispatcher components in EL3
184 Apart from these files, we have some context related source files under ``BL1``
318 per-CPU data structures, which means that each CPU will have an array of pointers
368 During the warm bootup process, secondary CPUs have their secure context
504 Apart from the CPU context structure, we have another structure to manage some
/rk3399_ARM-atf/docs/security_advisories/
H A Dsecurity-advisory-tfv-7.rst39 (SDEI)`_. Also, the TF-A project does not have visibility of all
47 have a system performance impact, which varies for each CPU type and use-case.

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