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Searched refs:faw_bank (Results 1 – 3 of 3) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_memory_controller.c181 faw_bank, bus_rd_to_rd, bus_rd_to_wr, bus_wr_to_rd; in configure_ddr_sched_ctrl_regs() local
285 faw_bank = 1; // always 1 because we always have 4 bank DDR. in configure_ddr_sched_ctrl_regs()
288 faw_bank << AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAWBANK_OFST | in configure_ddr_sched_ctrl_regs()
/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_memory_controller.c180 faw_bank, bus_rd_to_rd, bus_rd_to_wr, bus_wr_to_rd; in configure_ddr_sched_ctrl_regs() local
284 faw_bank = 1; // always 1 because we always have 4 bank DDR. in configure_ddr_sched_ctrl_regs()
287 faw_bank << AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAWBANK_OFST | in configure_ddr_sched_ctrl_regs()
/rk3399_ARM-atf/plat/intel/soc/stratix10/soc/
H A Ds10_memory_controller.c209 faw_bank, bus_rd_to_rd, bus_rd_to_wr, bus_wr_to_rd; in configure_ddr_sched_ctrl_regs() local
313 faw_bank = 1; // always 1 because we always have 4 bank DDR. in configure_ddr_sched_ctrl_regs()
316 faw_bank << S10_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAWBANK_OFST | in configure_ddr_sched_ctrl_regs()