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Searched refs:ctr_reg (Results 1 – 1 of 1) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_clock_manager.c547 uint32_t ctr_reg = 0U; in get_mpu_clk() local
563 ctr_reg = CLKMGR_ALTERA(CORE01CTR); in get_mpu_clk()
567 ctr_reg = CLKMGR_ALTERA(CORE2CTR); in get_mpu_clk()
571 ctr_reg = CLKMGR_ALTERA(CORE3CTR); in get_mpu_clk()
579 clock /= 1 + (mmio_read_32(ctr_reg) & CLKMGR_PLLCX_DIV_MSK); in get_mpu_clk()