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Searched refs:config_ddr_size (Results 1 – 1 of 1) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_ddr.c319 phys_size_t config_ddr_size; in agilex5_ddr_init() local
405 config_ddr_size = 0x80000000; in agilex5_ddr_init()
409 if (config_ddr_size != hw_ddr_size) { in agilex5_ddr_init()
410 WARN("DDR: DDR size configured is (%lld MiB)\n", config_ddr_size >> 20); in agilex5_ddr_init()
414 if (config_ddr_size > hw_ddr_size) { in agilex5_ddr_init()