Searched refs:bw_ratio_extended (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/plat/intel/soc/agilex5/soc/ |
| H A D | agilex5_memory_controller.c | 180 bw_ratio_extended, auto_precharge = 0, act_to_act_bank, faw, in configure_ddr_sched_ctrl_regs() local
273 bw_ratio_extended = ((ADP_DDRIOCTRL_IO_SIZE(data) == 0) ? 1 : 0); in configure_ddr_sched_ctrl_regs()
276 bw_ratio_extended << DDRMODE_BWRATIOEXTENDED_OFST | in configure_ddr_sched_ctrl_regs()
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| /rk3399_ARM-atf/plat/intel/soc/agilex/soc/ |
| H A D | agilex_memory_controller.c | 179 bw_ratio_extended, auto_precharge = 0, act_to_act_bank, faw, in configure_ddr_sched_ctrl_regs() local
272 bw_ratio_extended = ((ADP_DDRIOCTRL_IO_SIZE(data) == 0) ? 1 : 0); in configure_ddr_sched_ctrl_regs()
275 bw_ratio_extended << DDRMODE_BWRATIOEXTENDED_OFST | in configure_ddr_sched_ctrl_regs()
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| /rk3399_ARM-atf/plat/intel/soc/stratix10/soc/ |
| H A D | s10_memory_controller.c | 208 bw_ratio_extended, auto_precharge = 0, act_to_act_bank, faw, in configure_ddr_sched_ctrl_regs() local
301 bw_ratio_extended = ((ADP_DDRIOCTRL_IO_SIZE(data) == 0) ? 1 : 0); in configure_ddr_sched_ctrl_regs()
304 bw_ratio_extended << DDRMODE_BWRATIOEXTENDED_OFST | in configure_ddr_sched_ctrl_regs()
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