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Searched refs:VCP_R_CFGREG_CORE0 (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/vcp/mt8196/
H A Dvcp_reg.h37 #define VCP_R_CFGREG_CORE0 (MTK_VCP_REG_BASE + 0x20a000) macro
39 #define VCP_R_CORE0_STATUS (VCP_R_CFGREG_CORE0 + 0x0070)
41 #define CORE0_R_GPR5 (VCP_R_CFGREG_CORE0 + 0x0054)
43 #define CORE0_R_GPR6 (VCP_R_CFGREG_CORE0 + 0x0058)
/rk3399_ARM-atf/plat/mediatek/drivers/vcp/rv/
H A Dvcp_common.c29 MAP_REGION_FLAT(VCP_R_CFGREG_CORE0, MTK_VCP_REG_BANK_SIZE,