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Searched refs:UMCTL_BASE_CH (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/dmc/
H A Dsuspend.c86 configs->low_power[ch].pwrctl = mmio_read_32(UMCTL_BASE_CH(ch) + DDRCTL_PWRCTL); in exit_low_power()
87 mmio_clrbits_32(UMCTL_BASE_CH(ch) + DDRCTL_PWRCTL, in exit_low_power()
90 while ((mmio_read_32(UMCTL_BASE_CH(ch) + DDRCTL_STAT) & CTL_OPERATING_MODE_MASK) != in exit_low_power()
125 mmio_read_32(UMCTL_BASE_CH(ch) + DDRCTL_CLKGATECTL) & 0x3f; in exit_low_power()
138 mmio_clrsetbits_32(UMCTL_BASE_CH(ch) + DDRCTL_CLKGATECTL, in resume_low_power()
165 mmio_write_32(UMCTL_BASE_CH(ch) + DDRCTL_PWRCTL, configs->low_power[ch].pwrctl); in resume_low_power()
/rk3399_ARM-atf/plat/rockchip/rk3576/
H A Drk3576_def.h148 #define UMCTL_BASE_CH(n) (DDRCTL0_BASE + ((n) * 0x1000000)) macro