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Searched refs:TEGRA_SCRATCH_BASE (Results 1 – 6 of 6) sorted by relevance

/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/
H A Dplat_secondary.c63 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO, in plat_secondary_setup()
65 assert(mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO) == addr_low); in plat_secondary_setup()
66 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI, in plat_secondary_setup()
68 assert(mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI) == addr_high); in plat_secondary_setup()
69 mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV72_LO, in plat_secondary_setup()
71 assert(mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV72_LO) == (uint32_t)tzdram_addr); in plat_secondary_setup()
72 mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV72_HI, in plat_secondary_setup()
74 assert(mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV72_HI) == (uint32_t)src_len_bytes); in plat_secondary_setup()
H A Dplat_setup.c125 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x1000U, /* 4KB */
374 val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_HI_ADDR) & in plat_get_bl31_params()
377 val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_LO_ADDR); in plat_get_bl31_params()
389 val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_HI_ADDR) & in plat_get_bl31_plat_params()
392 val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_LO_ADDR); in plat_get_bl31_plat_params()
H A Dplat_psci_handlers.c139 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val); in tegra_soc_pwr_domain_suspend()
/rk3399_ARM-atf/plat/nvidia/tegra/drivers/memctrl/
H A Dmemctrl_v2.c161 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_LO, in tegra_mc_save_context()
163 assert(mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_LO) in tegra_mc_save_context()
165 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_HI, in tegra_mc_save_context()
167 assert(mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_HI) in tegra_mc_save_context()
/rk3399_ARM-atf/plat/nvidia/tegra/include/t194/
H A Dtegra_def.h218 #define TEGRA_SCRATCH_BASE U(0x0C390000) macro
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/drivers/se/
H A Dse.c401 mmio_write_32((uint32_t)(TEGRA_SCRATCH_BASE + scratch_offset), in tegra_se_save_sha256_pmc_scratch()